Richard W Doing, 621408 Acres Way, Raleigh, NC 27614

6438671, Aug 20, 2002

Jul 1, 1999

09/346206

Richard William Doing - Rochester MN
Ronald Nick Kalla - Zumbro Falls MN
Stephen Joseph Schwinn - Lakeville MN
Edward John Silha - Austin TX
Kenichi Tsuchiya - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 1206

711173, 711202, 712229

A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution.

6829684, Dec 7, 2004

Jun 20, 2002

10/175626

Richard William Doing - Rochester MN
Ronald Nick Kalla - Zumbro Falls MN
Stephen Joseph Schwinn - Lakeville MN
Edward John Silha - Austin TX
Kenichi Tsuchiya - Rochester MN

International Business Machines Corporation - Armonk NY

G06F 1214

711152, 711153, 711202, 712229, 712244

A real address range check mechanism verifies real addresses generated in a computer system which translates real addresses from effective addresses, some of the effective addresses being real addresses not requiring translation. The system has at least two operating modes. In one mode, the range checking mechanism generates an error signal responsive to detecting a real address outside a predetermined range, and in the other operating mode no error signal is generated. Preferably, the computer systems hardware resources, including real address space, is logically partitioned, partitioning being managed by an ultra-privileged process called a hypervisor. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, real address range checking error signals being disabled in the hypervisor state.

6993640, Jan 31, 2006

Sep 23, 2004

10/948776

Richard William Doing - Rochester MN, US
Ronald Nick Kalla - Zumbro Falls MN, US
Stephen Joseph Schwinn - Lakeville MN, US
Edward John Silha - Austin TX, US
Kenichi Tsuchiya - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 9/50

712200, 712 43, 712229, 718200

A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.

7281120, Oct 9, 2007

Mar 26, 2004

10/810235

James N. Dieffenderfer - Apex NC, US
Richard W. Doing - Raleigh NC, US
Brian M. Stempel - Raleigh NC, US
Steven R. Testa - Durham NC, US
Kenichi Tsuchiya - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 9/30

712219, 712235

A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

7305586, Dec 4, 2007

Apr 25, 2003

10/424485

Richard William Doing - Raleigh NC, US
Michael Stephen Floyd - Austin TX, US
Ronald Nick Kalla - Round Rock TX, US

International Business Machines Corporation - Armonk NY

G06F 11/00

714 28, 714 35

A microprocessor includes an externally accessible port and a serial communication bus connected to the port. An execution pipeline of the processor includes a pipeline satellite circuit coupling the pipeline to the bus. The satellite enables an external agent to provide an instruction directly to the pipeline via the serial bus. A dedicated register and register satellite circuit couple the register to the communication bus. The execution pipeline can access the dedicated register during execution of the instruction. In this manner, the satellite circuits enable the external agent to access architected state. The communication bus enables access to the satellites while a system clock to the processor remains active. In one embodiment, the pipeline satellite accesses the pipeline “downstream” of the decode stage such that the set of instructions that may be “rammed” into the pipeline is not limited to the set of instructions that the decode stage can generate.

7321954, Jan 22, 2008

Aug 11, 2004

10/915982

James N. Dieffenderfer - Apex NC, US
Richard W. Doing - Raleigh NC, US
Brian E. Frankel - Morrisville NC, US
Kenichi Tsuchiya - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 13/16
G06F 13/00

711134, 711133, 711136, 711160

An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

7437543, Oct 14, 2008

Apr 19, 2005

11/109001

Richard William Doing - Raleigh NC, US
Brett Olsson - Cary NC, US
Kenichi Tsuchiya - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 9/40

712240, 712238

A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

7558948, Jul 7, 2009

Sep 20, 2004

10/946465

Anthony J. Bybell - Carrboro NC, US
Richard W. Doing - Raleigh NC, US
David D. Dukro - Cary NC, US

International Business Machines Corporation - Armonk NY

G06F 9/00
G06F 9/44

712241, 712224

A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.