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Richard A Swetz, 60Durham, CT

Richard Swetz Phones & Addresses

Durham, CT   

Carmel, NY   

Los Altos, CA   

New York, NY   

69 Plum Rd, Mahopac, NY 10541    845-6214542   

Mount Kisco, NY   

Hawthorne, NY   

Mapleton, ND   

69 Plum Rd, Mahopac, NY 10541    914-4133299   

Work

Position: Administration/Managerial

Education

Degree: Graduate or professional degree

Emails

Mentions for Richard A Swetz

Publications & IP owners

Us Patents

Methods For Routing Packets On A Linear Array Of Processors

US Patent:
6961782, Nov 1, 2005
Filed:
Mar 14, 2000
Appl. No.:
09/525707
Inventors:
Monty M. Denneau - Brewster NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F015/173
US Classification:
709241, 370351, 370380, 370400, 712 11
Abstract:
There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

Methods For Routing Packets On A Linear Array Of Processors

US Patent:
7477608, Jan 13, 2009
Filed:
Jul 21, 2005
Appl. No.:
11/186693
Inventors:
Monty M. Denneau - Brewster NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/26
H04L 12/66
G06F 15/00
US Classification:
370241, 370353, 370380, 370400, 712 11
Abstract:
There is provided a method for routing packets on a linear of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.

Efficient Probabilistic Duplicate Packet Detector In Computer Networks

US Patent:
7619993, Nov 17, 2009
Filed:
Nov 1, 2005
Appl. No.:
11/264529
Inventors:
Carl A. Bender - Highland NY, US
Fu Chung Chang - Rhinebeck NY, US
Kevin J. Gildea - Bloomington NY, US
Rama J. Govindaraju - Hopewell Junction NY, US
Jay R. Herring - Hyde Park NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/28
G01R 31/08
G06F 11/00
G08C 15/00
H04J 1/16
H04J 3/14
H04L 1/00
H04L 12/26
G08C 25/00
G06F 15/16
US Classification:
370256, 370252, 714799, 709217
Abstract:
In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Power Throttling Of Collections Of Computing Elements

US Patent:
8001401, Aug 16, 2011
Filed:
Jun 26, 2007
Appl. No.:
11/768752
Inventors:
Ralph E. Bellofatto - Ridgefield CT, US
Paul W. Coteus - Yorktown Heights NY, US
Paul G. Crumley - Yorktown Heights NY, US
Alan G. Gara - Mount Kidsco NY, US
Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Cortlandt Manor NY, US
Mark G. Megerian - Rochester MN, US
Martin Ohmacht - Yorktown Heights NY, US
Don D. Reed - Mantorville MN, US
Richard A. Swetz - Mahopac NY, US
Todd Takken - Brewster NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/26
US Classification:
713320, 713300, 713310, 713321, 713322, 713323, 713324, 713330, 713340
Abstract:
An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Efficient Probabilistic Duplicate Packet Detector In Computer Networks

US Patent:
8031639, Oct 4, 2011
Filed:
Sep 17, 2009
Appl. No.:
12/561669
Inventors:
Carl A. Bender - Highland NY, US
Fu Chung Chang - Rhinebeck NY, US
Kevin J. Gildea - Bloomington NY, US
Rama K. Govindaraju - Hopewell Junction NY, US
Jay R. Herring - Hyde Park NY, US
Peter H. Hochschild - New York NY, US
Richard A. Swetz - Mahopac NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/28
H04L 1/00
H04L 12/26
G01R 31/08
G06F 11/00
G06F 15/16
G08C 15/00
G08C 25/00
H04J 1/16
H04J 3/14
US Classification:
370256, 370252, 714799, 709217
Abstract:
In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.

Global Synchronization Of Parallel Processors Using Clock Pulse Width Modulation

US Patent:
8412974, Apr 2, 2013
Filed:
Jan 29, 2010
Appl. No.:
12/696764
Inventors:
Dong Chen - Yorktown Heights NY, US
Matthew R. Ellavsky - Rochester MN, US
Ross L. Franke - Rochester MN, US
Alan Gara - Yorktown Heights NY, US
Thomas M. Gooding - Rochester MN, US
Rudolf A. Haring - Yorktown Heights NY, US
Mark J. Jeanson - Rochester MN, US
Gerard V. Kopcsay - Yorktown Heights NY, US
Thomas A. Liebsch - Sious Falls SD, US
Daniel Littrell - Carmel NY, US
Martin Ohmacht - Yorktown Heights NY, US
Don D. Reed - Rochester MN, US
Brandon E. Schenck - Rochester MN, US
Richard A. Swetz - Mahopac NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/04
G06F 1/12
G06F 15/16
US Classification:
713375, 713400, 713500, 713501, 713600
Abstract:
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Ram Based Implementation For Scalable, Reliable High Speed Event Counters

US Patent:
2010002, Feb 4, 2010
Filed:
Jul 31, 2008
Appl. No.:
12/183748
Inventors:
Carl Alfred Bender - Highland NY, US
Peter Heiner Hochschild - New York NY, US
Ashutosh Misra - Lucknow, IN
Richard Swetz - Mahopac NY, US
International Classification:
H03K 21/00
US Classification:
377 49
Abstract:
There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

Ram Based Implementation For Scalable, Reliable High Speed Event Counters

US Patent:
2013017, Jul 4, 2013
Filed:
Feb 25, 2013
Appl. No.:
13/776687
Inventors:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY, US
Peter Heiner Hochschild - New York NY, US
Ashutosh Misra - Uttar Pradesh, IN
Richard Swetz - Mahopac NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H03K 21/00
US Classification:
377 49
Abstract:
There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.

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