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Ritu Gupta, 44Cupertino, CA

Related to:
Monika Gupta 49 Shilpi Gupta 41 Shivangi Gupta 30 Surbhi Gupta 40 Akhil Gupta

Ritu Gupta Phones & Addresses

Cupertino, CA   

Sunnyvale, CA   

3650 Buckley St #302, Santa Clara, CA 95051    408-2446842   

San Francisco, CA   

Champaign, IL   

22378 Salem Ave APT C, Cupertino, CA 95014    408-2534791   

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Ritu Gupta resumes & CV records

Resumes

Ritu Gupta Photo 32

Law Student

Location:
Greater Boston Area
Industry:
Law Practice
Work:
WilmerHale - Boston, MA May 2013 - Jul 2013
Summer Associate NASA, Office of the General Counsel - Washington, D.C. Jun 2012 - Aug 2012
Law Student Intern Superior Court of California - Oakland, CA May 2011 - Jul 2011
Law Student Intern Law Office of Anand Ahuja, Esq. - Queens, NY Jun 2010 - Dec 2010
Legal Intern Phillips Education Systems - Manhasset, NY Jan 2010 - Aug 2010
Chemistry Teacher
Education:
Harvard Law School 2011 - 2014
JD Columbia University in the City of New York 2007 - 2009
MA, Chemistry Barnard College 2003 - 2007
B.A., Biochemistry
Ritu Gupta Photo 33

Ritu Gupta

Location:
United States
Ritu Gupta Photo 34

Ritu Gupta

Location:
United States
Ritu Gupta Photo 35

Ritu Gupta

Location:
United States
Ritu Gupta Photo 36

Ritu Gupta

Location:
United States

Publications & IP owners

Us Patents

Scalable Address Decoding Scheme For Cxl Type-2 Devices With Programmable Interleave Granularity

US Patent:
2023008, Mar 23, 2023
Filed:
Sep 17, 2021
Appl. No.:
17/478828
Inventors:
- Santa Clara CA, US
Ritu Gupta - Cupertino CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/38
G06F 13/42
G06F 13/40
G06F 13/16
G06F 9/46
Abstract:
Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.

High-Bandwidth, Low-Latency, Isochoronous Fabric For Graphics Accelerator

US Patent:
2019004, Feb 7, 2019
Filed:
Dec 14, 2017
Appl. No.:
15/842562
Inventors:
- Santa Clara CA, US
Aravindh Anantaraman - Santa Clara CA, US
Ritu Gupta - Santa Clara CA, US
Robert Adler - Santa Clara CA, US
International Classification:
G06F 13/16
G06F 13/42
G06F 12/14
Abstract:
Techniques are provided for low-latency, high bandwidth graphics accelerator die and memory system. In an example, a graphics accelerator die can include a plurality of memory blocks for storing graphic information, a display engine configured to request and receive the graphic information from the plurality of memory blocks for transfer to a display, a graphics engine configured to generate and transfer the graphic information to the plurality of memory blocks, and a high-bandwidth, low-latency isochronous fabric configured to arbitrate the transfer and reception of the graphic information.

Possible Relatives

David Gupta  Dalip K Gupta  Aakash Gupta  Deborah F Gupta  Deep S Gupta  Deepa Gupta  Deepti Gupta  Ritu R Singh  Ritu Rai  Ritu Sethi 

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