Roger D Allen, 80106 Clover Ct, Longwood, FL 32750

6825843, Nov 30, 2004

Nov 22, 2002

10/302411

Roger L. Allen - San Jose CA
Harold Robert Feldman Zatz - Palo Alto CA

NVIDIA Corporation - Santa Clara CA

G06T 1500

345522, 345503, 345426, 345614, 345506, 712233, 712241, 712245, 712247

A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.

7122154, Oct 17, 2006

Dec 23, 1994

08/363615

Glenn C. Forrester - Oakland CA, US
Roger Allen - Benicia CA, US
Roger Herrera - Oakland CA, US
Daniel S. Goldberger - Boulder CO, US
James R. Braig - Oakland CA, US

Intoximeters, Inc. - St. Louis MO

G01N 33/497

422 84, 422 93, 128719

A method and infrared sensing device for determining the concentration of alveolar alcohol in a breath sample exhaled by a subject into an infrared sensing device. The presence of alcohol from the upper respiratory tract of the subject is detected by continuously monitoring alcohol and carbon dioxide, normalizing alcohol values with respect to carbon dioxide, calculating a difference between normalized alcohol concentration and carbon dioxide concentration over time, integrating (summing) the difference, and comparing the integrated difference with a threshold. This technique accurately and consistently detects the presence of mouth alcohol in the sample before the presence of carbon dioxide which originates in deep lung breath.

7385607, Jun 10, 2008

Sep 10, 2004

10/938042

Rui M. Bastos - Porto Alegre, BR
Karim M. Abdalla - Menlo Park CA, US
Christian Rouet - San Rafael CA, US
Michael J. M. Toksvig - Palo Alto CA, US
Johnny S. Rhoades - Durham NC, US
Roger L. Allen - San Jose CA, US
Emmett M. Kilgariff - San Jose CA, US
Gary M. Tarolli - Concord MA, US
Brian Cabral - San Jose CA, US
Craig Michael Wittenbrink - Palo Alto CA, US
Sean J. Treichler - Mountain View CA, US

NVIDIA Corporation - Santa Clara CA

G06F 15/16
G06F 15/80
G06T 1/20

345502, 345505, 345506

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.

7439979, Oct 21, 2008

Nov 10, 2004

10/985285

Roger L. Allen - San Jose CA, US
Chad D. Walker - San Jose CA, US
Rui M. Bestos - Porto Alegre, BR

NVIDIA Corporation - Santa Clara CA

G06T 1/20
G09G 5/36

345506, 345557

A shader having a cache memory for storing program instructions is described. The cache memory beneficially stores both current programming instructions for a fragment program being run and “look-ahead” programming instructions. The cache memory supports a scheduler that forms program commands that control programmable processing stations. The cache memory can store multiple programming instructions for a plurality of shaders. If the cache memory does not include the desired programming instructions, a miss is asserted and a scheduler (instruction processor) recovers the programming instructions to be run. Beneficially, the scheduler recovers additional programming instructions to support the look-ahead programming. The cache memory stores program instructions by cachelines, where each cacheline comprises a plurality of programming instructions. The cache memory can also store program identifiers.

7542042, Jun 2, 2009

Nov 10, 2004

10/985575

Roger L. Allen - San Jose CA, US
Rui M. Bastos - Porto Alegre, BR
Karim M. Abdalla - Menlo Park CA, US
Justin S. Legakis - Sunnyvale CA, US

NVIDIA Corporation - Santa Clara CA

G06T 1/20
G06F 15/80
G09G 5/377
G09G 5/397
G09G 5/00

345506, 345505, 345629

A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops through a texture processing stations to produce a fragment shader-processed background. Then, at least some of those pixels are merged with the video or images to produce complex video content. The resulting complex image is then made available for further processing.

7600155, Oct 6, 2009

Dec 13, 2005

11/302950

John R. Nickolls - Los Altos CA, US
Roger L. Allen - Lake Oswego OR, US
Brian K. Cabral - San Jose CA, US
Brett W. Coon - San Jose CA, US
Robert C. Keller - Palo Alto CA, US

NVIDIA Corporation - Santa Clara CA

G06F 11/00

714 38

A system has a graphics processing unit with a processor to monitor selected criteria and circuitry to initiate the storage of execution state information when the selected criteria reaches a specified state. A memory stores execution state information. A central processing unit executes a debugging program to analyze the execution state information.

7711990, May 4, 2010

Dec 13, 2005

11/302952

John R. Nickolls - Los Altos CA, US
Roger L. Allen - Lake Oswego OR, US
Brian K. Cabral - San Jose CA, US
Brett W. Coon - San Jose CA, US
Robert C. Keller - Palo Alto CA, US

Nvidia Corporation - Santa Clara CA

G06F 11/00

714 37

A system includes a graphics processing unit with a processor responsive to a debug instruction that initiates the storage of execution state information. A memory stores the execution state information. A central processing unit executes a debugging program to analyze the execution state information.

7852340, Dec 14, 2010

Dec 14, 2007

11/957358

Rui M. Bastos - Rua Luzitana, BR
Karim M. Abdalla - Menlo Park CA, US
Christian Rouet - San Rafael CA, US
Michael J.M. Toksvig - Palo Alto CA, US
Johnny S Rhoades - Durham NC, US
Roger L. Allen - San Jose CA, US
Emmett M. Kilgariff - San Jose CA, US
Gary M. Tarolli - Concord MA, US
Brian Cabral - San Jose CA, US
Craig Michael Wittenbrink - Palo Alto CA, US
Sean J. Treichler - Mountain View CA, US

NVIDIA Corporation - Santa Clara CA

G06F 15/80
G06T 15/50
G06T 15/00

345505, 345426, 345522

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.