Roger S Rutter, 82953 Hollister Rd, Owego, NY 13827

6611159, Aug 26, 2003

Feb 19, 2002

10/078224

Louis C. Milano - Endwell NY
Eric E. Retter - Warren Center PA
Roger S. Rutter - Owego NY
Michael P. Vachon - Johnson City NY

International Business Machines Corporation - Armonk NY

H03L 706

327147, 327156, 327159, 331 11

An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.

6677513, Jan 13, 2004

May 29, 1998

09/087534

Roger Sherman Rutter - Owego NY

International Business Machines Corporation - Armonk NY

G10H 106

84622

An audible tone is generated and attenuated over a wide frequency range, such as throughout the human audible range, the tone selectively being of short duration. During a tone period a digital representation of the sine of a requested tone frequency and amplitude is generated. During an attenuation period a digital representation of a moderately disturbed but continuous sine of decreasing amplitude is generated. During a decay period a digital representation of a continuous function which decays to zero from the zero approach point of the sine half wave is generated. During the attenuation period, at zero crossings, the amplitude value is multiplied by a fractional constant; within zero passing zones, the amplitude between subsequent samples is incremented by temporally reduced values to further attenuate the tone and accumulate a bank of accumulated reductions in increments; and while approaching zero crossings, a sine wave of maximum amplitude equal to the amplitude at the beginning of the prior quadrant minus the bank of accumulated reductions in increments during said prior quadrant is generated; and during a decay period, a digital representation of a continuous function which decays to zero amplitude is generated.

6898327, May 24, 2005

Mar 23, 2000

09/535002

David A. Hrusecky - Johnson City NY, US
Roger S. Rutter - Owego NY, US

International Business Machines Corporation - Armonk NY

G06K009/40

382260, 382275, 348606

Flickering artifacts are removed from a displayed image by storing digital luminance values in a compressed form using disallowed luminance values clipped from a range of luminance values to encode run lengths of identical values of truncated luminance values and bits corresponding to bits truncated from the luminance values. A correction value is derived from a filter transfer function computed by summing an increase in correction value above a threshold within a range of luminance differences with a maximum change in correction value in each lower range, this providing a piecewise linear substantially quadratic transfer function without discontinuities that would engender other image artifacts. The non-linearity of the transfer function is this adaptive to different image conditions and types in regions of respective image planes and the correction factors implemented by the transfer function are freely adjustable to accommodate, for example, different scanning standards and display refresh rates.

6996186, Feb 7, 2006

Feb 22, 2002

10/080745

Agnes Y. Ngai - Endwell NY, US
Roger S. Rutter - Oswego NY, US
Robert L. Woodard - Newark Valley NY, US

International Business Machines Corporation - Armonk NY

H04N 7/12
H04N 11/02

37524029

A technique is provided for programmably horizontally filtering pixel values of frames of a plurality of video frames. The technique includes, in one embodiment, passing pixel values through a real-time horizontal filter disposed as preprocessing logic of a video encode system. The horizontal filter is programmable and includes a filter coefficients buffer for holding multiple sets of filter coefficients. The horizontal filter programmably employs the multiple sets of filter coefficients to selectively perform spatial noise filtering, or spatial noise filtering and image scaling on the pixels. The filter coefficients are also programmable and may be changed dynamically and repeatedly, with changes being applied at frame boundaries. When performing image scaling, multiple sets of filter coefficients are employed.

4571451, Feb 18, 1986

Jun 4, 1984

6/616869

Ralph Linsker - Scarsdale NY
Roger S. Rutter - Vestal NY

International Business Machines Corporation - Armonk NY

H05K 100

174 685

A method for establishing interconnections in the vicinity of congested clusters of pins in a printed circuit using an extended escape region in combination with an escape region and a global region. The extended escape region includes wire path segments in one signal plane of a plane pair which may enter the extended escape region from the escape region in a direction angularly disposed to the predominant direction of wiring in that plane. All wire segments exit the extended escape region to said global region in the predominant direction for the signal plane on which the interconnection is disposed.

4689441, Aug 25, 1987

Apr 5, 1985

6/720127

Carroll J. Dick - Dryden NY
Ralph Linsker - Scarsdale NY
Roger S. Rutter - Vestal NY
David L. Thomas - Vestal NY

International Business Machines Corporation - Armonk NY

H05K 100

174 685

In printed circuit boards having dense printed connections, cross talk noise immunity is significantly improved by preferentially routing adjacent to one another serially connected conductors of the same net rather than conductors of different nets. By such routing inter-net cross talk is reduced while the resultant intra-net cross talk is maintained at tolerable levels.

5963728, Oct 5, 1999

Aug 14, 1996

8/696555

David James Hathaway - Underhill Center VT
Roger Sherman Rutter - Johnson City NY

International Business Machines Corporation - Armonk NY

G06F 1750

39550004

A method of designing the clocking circuitry of an integrated circuit chip. The load sinks are assigned to clock nets, each clock net having less then a maximum load. The first step is selecting a pair of clock nets for improvement. Next, a subset of the load sinks of the pair of clock nets are assigned to each clock net. Thereafter, the unassigned load sinks are assigned in all possible combinations to each of the pair of clock nets. A penalty function for each load sink assignment, and the assignment having the best penalty function is kept.