Roger J Yerdon, 6760 South Ave, Pleasant Valley, NY 12569

6908830, Jun 21, 2005

Jun 23, 2003

10/604028

Andrew Lu - Poughkeepsie NY, US
Donald M. Odiwo - Wappingers Falls NY, US
Roger J. Yerdon - Pleasant Valley NY, US

International Business Machines Corporation - Armonk NY

H01L021/66

438426, 438401, 438975

A method of repeatedly exposing a pattern across a wafer in a sequential stepping process is disclosed. The pattern that is exposed includes at least one alignment mark. Each time the exposing process is repeated, the current exposure overlaps a portion of the wafer where the pattern was previously exposed and thereby erases a previously exposed alignment mark by re-exposing an area of the wafer where the previously exposed alignment mark was located. After the exposing process is repeated across the wafer, alignment marks remain only in the last exposed areas of the wafer.

8039366, Oct 18, 2011

Feb 19, 2009

12/388851

Karen L. Holloway - Poughkeepsie NY, US
Holly LaFerrara - Wappingers Falls NY, US
Alexander L. Martin - Hopewell Junction NY, US
Martin E. Powell - Peekskill NY, US
Timothy J. Wiltshire - Fishkill NY, US
Roger J. Yerdon - Pleasant Valley NY, US

International Business Machines Corporation - Armonk NY

H01L 21/00
H01L 23/544

438462, 257797

A method and apparatus includes an integrated circuit device, and at least one alignment mark on the integrated circuit device, the alignment mark comprises a first coded region, a second coded region adjacent the first coded region, and a third coded region adjacent the second coded region, the second coded region located between the first coded region and the third coded region, and markings on the first coded region and the third coded region being identical.

8423945, Apr 16, 2013

May 18, 2010

12/782337

Jeanne P. Bickford - Essex Junction VT, US
Allan O. Cruz - Colchester VT, US
Michelle Gill - Grand Isle VT, US
Howard S. Landis - Underhill VT, US
Donald J. Samuels - Silverthorne CO, US
Roger J. Yerdon - Pleasant Valley NY, US

International Business Machines Corporation - Armonk NY

G06F 17/50
G06F 9/455

716132, 716122

Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

2007010, May 17, 2007

Nov 16, 2005

11/164266

Michael Lane - Cortlandt Manor NY, US
Christopher Muzzy - Burlington VT, US
Roger Yerdon - Pleasant Valley NY, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

H01L 23/544
H01L 21/78

257797000, 438462000

A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line site for alignment of the dicing blade. A plurality of rectangular elements is situated about the periphery of the alignment mark and populated with via bar structures that are interconnected at each level of the wafer, and laid in a serpentine fashion throughout each element to expose more of the via bar structure surface area to propagating cracks. The rectangular elements are formed of different sizes to expose more surface area to propagating cracks. A plurality of square, metal-level structures is formed in the area between the cross-shaped structure and the peripherally placed, rectangular elements.

2010019, Jul 29, 2010

Jan 27, 2009

12/360132

Christopher P. Ausschnitt - Boston MA, US
Jaime D. Morillo - Beacon NY, US
Jed H. Rankin - Richmond VT, US
Roger J. Yerdon - Pleasant Valley NY, US

International Business Machines Corporation - Armonk NY

G03F 1/00
G06F 7/20

430 5, 430 30

A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation.

5304441, Apr 19, 1994

Dec 31, 1992

7/999439

Donald J. Samuels - Yorktown Heights NY
Roger J. Yerdon - Pleasant Valley NY

International Business Machines Corporation - Armonk NY

G03F 702
G03F 720

430 30

A method of adjusting exposure of an energy beam to a lithographic resist sensitive to the energy beam, which method comprises determining where in a pattern to be exposed the energy level will exceed a critical thermal level, and adjusting the pattern and kind of exposure of the resist where the critical level is exceeded. One technique is to adjust the level exposure of the resist to a lower level equal to or less than the critical level with repeated exposures of the pattern in areas where the critical level is exceeded. The energy level monitored can be a thermal level measured as a temperature of the resist. A second technique is to adjust the exposure level by modifying the pattern and duration of exposure of the resist to a longer duration providing exposures equal to or less than the critical level with the modified pattern of exposures of the pattern in areas where the critical level is exceeded.

2015016, Jun 11, 2015

Dec 9, 2013

14/100297

- Armonk NY, US
Jaime D. Morillo - Cedar Park TX, US
Roger J. Yerdon - Pleasant Valley NY, US

International Business Machines Corporation - Armonk NY

H01L 21/66
G06F 17/50

A method of determining stitching errors in multiple lithographically exposed fields on a semiconductor layer during a semiconductor manufacturing process is provided. The method may include receiving a predetermined design distance corresponding to a plurality of petals associated with the multiple lithographically exposed fields and identifying a blossom within a single field-of-view (FOV) of a metrology tool, where the blossom is formed by a non-overlapping abutment of corners corresponding to the multiple lithographically exposed fields. The blossom may include the plurality of petals associated with the multiple lithographically exposed fields. Petal position errors may then be calculated based on both a coordinate position for each of the plurality of petals within the blossom and the predetermined design distance, whereby the calculated petal position errors are indicative of stitching errors for the multiple lithographically exposed fields.