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Ronald H Cieslak, 86Keeneyville, IL

Known as:
Leslie Browncieslak Gay Leslie G Cieslak Ronal H Cieslak Ron Cieslak Leslie Brown Cieslak Gay Leslie Brown Gay Gay K
Related to:
Grant R Cieslak

Ronald Cieslak Phones & Addresses

Roselle, IL   

Washington, DC   

1734 N Wells St APT 5, Chicago, IL 60614   

1734 Wells St, Chicago, IL 60614   

400 Albion Ave, Roselle, IL 60172    630-3037960   

Work

Position: Protective Service Occupations

Education

Degree: High school graduate or higher

Emails

r***[email protected]
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Ronald Cieslak resumes & CV records

Resumes

Ronald Cieslak Photo 11

Ronald Cieslak

Location:
Washington, DC
Industry:
Oil & Energy
Work:
Xx Jan 2015 - Jun 2015
Xx Cbp Engineering Corp's Energy Services Division Aug 2014 - Jan 2015
Vice President of Operations Dte Energy 2005 - Sep 2014
Project and Construction Management
Skills:
Management, Process Scheduler, Project Management, Construction, Primavera P6, Project Coordination, Supervisory Skills, Contract Management, Construction Management, Gas, Pre Construction, Subcontracting, Construction Safety, Change Orders, Budgets
Ronald Cieslak Photo 12

Ronald Cieslak

Location:
United States

Publications & IP owners

Us Patents

X.times.y Bit Array Multiplier/Accumulator Circuit

US Patent:
4575812, Mar 11, 1986
Filed:
May 31, 1984
Appl. No.:
6/615989
Inventors:
Kevin L. Kloker - Arlington Heights IL
Ronald H. Cieslak - Chicago IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 752
US Classification:
364760
Abstract:
An X. times. Y bit array multiplier/accumulator circuit is provided for adding an input number having (X+Y) bits to an (X+Y) bit product of an X bit number and a Y bit number, where X and Y are integers. Modified Booth's algorithm is implemented with an array structure which maintains a regular and systematic structure. The array structure uses adders and multiplexers in a predetermined column and row arrangement. Propagation delay is minimized while utilizing the modified Booth's algorithm by using a sum skipping technique and by using inverting logic properties of adders. Sign bit extension is provided by additional logic circuitry and signed/unsigned modes of operation are provided.

Exclusive Or/Nor Gate Having Cross-Coupled Transistors

US Patent:
4713790, Dec 15, 1987
Filed:
Jul 31, 1985
Appl. No.:
6/760841
Inventors:
Kevin L. Kloker - Arlington Heights IL
Ronald H. Cieslak - Chicago IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 750
H03K 1921
US Classification:
364784
Abstract:
A CMOS exclusive OR/NOR gate is implemented with cross coupled transistors of the same conductivity type for simultaneously providing both logic signals. The logic gate is characterized by a pair of cross-coupled transistors of the same conductivity type coupled to the outputs thereof for selectively reinforcing the output logic level. One use of the exclusive OR/NOR gate is illustrated by coupling the gate to a switched logic circuit to provide a full adder. Transmission gate steering logic is used to further enhance circuit speed.

Wide Common Mode Range Analog Cmos Voltage Comparator

US Patent:
4598215, Jul 1, 1986
Filed:
Nov 3, 1983
Appl. No.:
6/548537
Inventors:
Melvin A. Schechtman - Schaumburg IL
Ronald H. Cieslak - Chicago IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 524
US Classification:
307355
Abstract:
An improved analog CMOS comparator circuit is described. The improved circuit incorporates an additional CMOS device in the output stage of a conventional differential comparator. The additional device compensates for current imbalances which occur at relatively high common mode voltages thus allowing the improved comparator to operate over a wider range of common mode input voltages.

Mos Full Adder Circuit

US Patent:
4583192, Apr 15, 1986
Filed:
Sep 30, 1983
Appl. No.:
6/538039
Inventors:
Ronald H. Cieslak - Chicago IL
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 750
US Classification:
364784
Abstract:
An MOS full adder circuit having a sum circuit portion and a carry circuit portion is provided. In an embodiment utilizing transistors of opposite conductivity type, both the sum and carry circuits are symmetrical, thereby simplifying the physical layout of the full adder during fabrication.

Possible Relatives

David M Cieslak  Daniel J Cieslak  Edward M Cieslak  Edwin F Cieslak  Eric P Cieslak  James E Cieslak  Jason E Cieslak  Ronald W Johnson  Ronald R Stamps  Ronald L Stancill 

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