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Ruben D Herrera, 60Hackensack, NJ

Ruben Herrera Phones & Addresses

Hackensack, NJ   

Keasbey, NJ   

Education

Degree: Doctor of Jurisprudence/Juris Doctor (J.D.) School / High School: Baylor University School of Law

Ranks

Licence: Texas - Eligible To Practice In Texas Date: 2005

Mentions for Ruben D Herrera

Career records & work history

Lawyers & Attorneys

Ruben Herrera Photo 1

Ruben Garza Herrera Jr. - Lawyer

Licenses:
Texas - Eligible To Practice In Texas 2005
Education:
Baylor University School of LawDegree Doctor of Jurisprudence/Juris Doctor (J.D.)Graduated 2005
Ruben Herrera Photo 2

Ruben Herrera - Lawyer

Specialties:
Criminal
ISLN:
1001189668
Admitted:
2022
Ruben Herrera Photo 3

Ruben Herrera - Lawyer

ISLN:
1000927828
Admitted:
2019

Ruben Herrera resumes & CV records

Resumes

Ruben Herrera Photo 50

Physician Office Assistant At Memorial Sloan-Kettering Cancer Center

Position:
Physician Office Assistant at Memorial Sloan-Kettering Cancer Center, Physician Office Assistant at Memorial Sloan-Kettering Cancer Center
Location:
United States
Industry:
Hospital & Health Care
Work:
Memorial Sloan-Kettering Cancer Center since Nov 2004
Physician Office Assistant
FedEx Jun 2004 - Nov 2004
Courier/Driver
Our Saviour Lutheran Summer Camp Jun 2003 - Sep 2004
Camp Counselor
United Artist Theater Circuit, Inc Jul 1997 - Dec 2002
Assistant Manager
Education:
Laguardia Community College 1997 - 2000
A.S., Business Administration
Laguardia Community College
Applied Associate's Degree, Business Administration
Interests:
professional networking, musical scout contacts, job opportunities
Honor & Awards:
MSKCC Department of Surgery Floater of the Year Award 2008
Ruben Herrera Photo 51

Ruben Herrera

Location:
United States
Ruben Herrera Photo 52

Ruben Herrera

Location:
United States
Ruben Herrera Photo 53

Ruben Herrera

Location:
Estados Unidos
Ruben Herrera Photo 54

Ruben Herrera

Location:
United States
Ruben Herrera Photo 55

Police Officer

Position:
Police Officer at Tucson Police Department
Location:
Tucson, Arizona
Industry:
Law Enforcement
Work:
Tucson Police Department - 1100 S Alvernon Rd since Jun 2008
Police Officer
US Army Sep 1997 - Sep 2008
Staff Sergeant
Ruben Herrera Photo 56

Stylist For Giorgio Armani Company

Location:
Greater New York City Area
Industry:
Retail
Education:
Fullerton College 2007 - 2011
Ruben Herrera Photo 57

Ruben Herrera

Work:
Remedy Staffing Dec 2013 to 2000 United Healthcare Mar 2013 to Oct 2013 Insight Global Sep 2011 to Feb 2013
Ensure of HIPAA rules and requlations are kept current for both myself and the member
Coventry Health Care Sep 2010 to Aug 2011 Blue Bell Creameries Mar 2006 to Jun 2009 JP Morgan Chase Mar 2005 to Dec 2005 One Source Jul 2003 to Mar 2005 Spherion Staffing Jul 2002 to Mar 2003
Education:
Quest College Nov 2009 to Jun 2010
Medical Billing and Coding

Publications & IP owners

Us Patents

Cmos Folding Amplifier Having High Resolution And Low Power Consumption

US Patent:
6480065, Nov 12, 2002
Filed:
Jun 4, 2001
Appl. No.:
09/873559
Inventors:
Ruben Herrera - Short Hills NJ
Sanjeev Ranganathan - New York NY
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03F 345
US Classification:
330253, 330 9
Abstract:
A folding differential amplifier includes a switching preamplifier used to select between first and second differential amplifiers as a function of an input signal. The switching preamplifier includes first and second outputs that are coupled together by a first shorting switch having an open phase and a closed phase. The first and second outputs are held at a steady state value during the closed phase of the shorting switch and allowed to vary during the open phase of the shorting switch. First and second differential amplifiers each have first and second outputs and the first output of the first differential amplifier is coupled to the second output of the second differential amplifier. Similarly, the second output of the first differential amplifier is coupled to the first output of the second differential amplifier. These cross coupled outputs form first and second amplifier outputs respectively. The first and second amplifier outputs of the can be coupled together by a second shorting switch having a closed phase and an open phase.

Gate Bootstrapped Cmos Sample-And-Hold Circuit

US Patent:
6525574, Feb 25, 2003
Filed:
Sep 6, 2001
Appl. No.:
09/947989
Inventors:
Ruben Herrera - Short Hills NJ
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G11C 2702
US Classification:
327 94, 327589
Abstract:
A sample and hold circuit to sample and hold a signal, includes a load capacitor to hold the signal, a switch to control the charging of said load capacitor, and a boost circuit to control the operation of said switch. The boost circuit is directly connected to the switch without another switch between the boost circuit and the switch.

Edge-Triggered Toggle Flip-Flop Circuit

US Patent:
6621319, Sep 16, 2003
Filed:
Sep 29, 1999
Appl. No.:
09/407535
Inventors:
Ruben Herrera - New York NY
Rahul Sarpeshkar - Cambridge MA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03K 3037
US Classification:
327221, 327199
Abstract:
An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.

Edge-Triggered Toggle Flip-Flop Circuit

US Patent:
6882198, Apr 19, 2005
Filed:
Jul 8, 2003
Appl. No.:
10/614178
Inventors:
Ruben Herrera - New York NY, US
Rahul Sarpeshkar - Cambridge MA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03K003/02
US Classification:
327197, 327208, 327218
Abstract:
An edge-triggered flip-flop circuit in which a pair of capacitors are alternately charged and discharged to voltages approximating supply rail values and, in combination of with a small number of switches, present high or low impedance paths for input signal transitions of a predetermined polarity to trigger state changes. In an alternative embodiment large switching capacitors are avoided in a circuit that employs a pair of pass-transistor configurations to connect respective capacitors to output terminals of a bistable device. The voltages on the capacitors track the corresponding bistable device output voltages when the input signal is in a given state (illustratively low), and store the value of the corresponding voltage when turned off by the (illustratively high) other state of the input signal. Then, the voltage on the capacitors and the selected input signal transition is used to effectively trigger a transition in the bistable device.

Spike-Triggered Asynchronous Finite State Machine

US Patent:
6292023, Sep 18, 2001
Filed:
Sep 29, 1999
Appl. No.:
9/407533
Inventors:
Ruben Herrera - New York NY
Rahul Sarpeshkar - Cambridge MA
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H03K 19173
G06F 738
US Classification:
326 46
Abstract:
A finite state machine in which n discrete states of the machine are encoded using a set of n bistable elements permitting simplified decoding of states. Transitions between discrete states are illustratively executed by selectively directing a bistable device to a 1 state using transition circuits activated by positive transitions of asynchronous spiking inputs. In one illustrative embodiment the positive transition is capacitively coupled to a switch that connects the complement output of a bistable element to ground, thereby causing the nominal output of that element to approach a voltage corresponding to a 1 state. In a second illustrative embodiment a pass transistor combination maintains a capacitor at the nominal output voltage of the bistable element in a 1 state until a spiking input signal arrives. A combination of the spiking input signal and the voltage on the capacitor connects the complement output of another bistable element to ground, thus switching that other bistable element.

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