Rune Adam Jensen, 561234 Lanterman Ln, La Canada Flintridge, CA 91011

6347326, Feb 12, 2002

Mar 2, 1999

09/260343

Rune Hartung Jensen - Sunnyvale CA
Hans Albert Spanjaart - Cupertino CA
Hans Adrianus Bouwmeester - Sunnyvale CA
Kenneth David Currie - Beuningen, NL

Philips Electronics North America Corporation - New York NY

G06F 752

708625, 708628

The operands of an NÃM bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less significant submultiples is assigned a positive sign. The product of each submultiple pair is sign extended to the width of the product (N+M), and the accumulation of these sign extended submultiple products provides the product of the original twos complement operands, in twos complement form.

6393572, May 21, 2002

Apr 28, 1999

09/300902

Dev Datta - Fremont CA
Rune H. Jensen - Sunnyvale CA
Calto Wong - Sunnyvale CA
Daisuke Takise - San Jose CA

Philips Electronics North America Corporation - New York NY

G06F 132

713322, 713601

In a master-slave configuration wherein a sleepmode activation is effected by the cessation of a clocking signal, the need for an analog device or auxiliary clock for detecting the cessation of the clocking signal is obviated by anticipating the cessation of the clock signal. Upon anticipating the cessation of the clock signal, the remaining clock signaling before cessation is used as required to effect a controlled power-down of the slave device. By eliminating the need for an analog clock cessation detector, the process tolerance constraints associated with analog circuitry can be avoided, the reliability and robustness of the design is improved, and the required testing is simplified, thereby reducing the cost of the device. In like manner, the elimination of an auxiliary clock generator reduces the cost and complexity of the device and system, and improves the device and systems overall reliability and testability. In accordance with this invention, the anticipation of the cessation of the clock signal is achieved by monitoring the communications among devices for commands that can be expected to affect the generation of the clock signal.

6426650, Jul 30, 2002

Dec 28, 1999

09/473538

Yves Dufour - Sunnyvale CA
Rune Hartung Jensen - Sunnyvale CA

Koninklijke Philips Electronics, N.V. - Eindhoven

H01L 2500

326 47, 326101, 326 9, 438 12, 438 14, 438 17, 365200

A method of manufacturing an integrated circuit having metal programmable logic cells. Metal programmable logic cells include transistors which, by varying routing of conductors in the metalization of the integrated circuit, may be connected in or disconnected from a logic path extending between the input and output of the cell. Transistors which are deselected by not being connected in the logic path are also decoupled from the supply rails. Generally speaking, deselected transistors can not be scan tested without substantial additional circuitry, as they do not form part of the logic path between the cell input and output to which the scan test circuitry is normally coupled. Decoupling transistors which are not in the logic path ensures that âstuck onâ faults, in which transistors are stuck in a conductive state, do not allow current to flow between the supply rails through these faulty transistors, thus avoiding hot spots and reliability problems. By preventing damage even in the event of a âstuck onâ fault, the need for extra test circuitry is avoided.

6434706, Aug 13, 2002

May 24, 1999

09/316983

Rune Hartung Jensen - Sunnyvale CA
Thomas ODwyer - Sunnyvale CA
Michael Gartlan - Sunnyvale CA

Koninklijke Philips Electronics N.V. - Eindhoven

G06F 106

713500, 713401, 713600, 713 61, 709400

A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock. By selecting the predetermined phase relationship appropriately, an optimal data transfer speed can be achieved.

6480967, Nov 12, 2002

May 21, 1999

09/316783

Rune Hartung Jensen - Sunnyvale CA
Michael Gartlan - Sunnyvale CA

Koninklijke Philips Electronics N.V. - Eindhoven

G06F 104

713600, 713400, 713500, 710 8, 710104, 712 15

A reset module operates in conjunction with a system clock module to provide a combination of reset and clock assertions that can be relied upon to reset conventional processing modules having a variety of reset architectures. A reset command initiates an assertion of the reset signal and an activation of all clocks at the system level. After a predetermined number of clock cycles, the system level clocks are deactivated, and then the reset signal is de-asserted. By providing multiple clock cycles with the reset signal asserted, processing modules having either asynchronous and synchronous reset will be reset. By disabling the clocks before de-asserting the reset signal, the likelihood of a timing hazard caused by an interaction of the reset signal and a clocking signal is reduced or eliminated.

6496035, Dec 17, 2002

Apr 6, 2001

09/828331

Rune Hartung Jensen - Sunnyvale CA
Yves Dufour - Sunnyvale CA

Koninklijke Philips Electronics N.V. - Eindhoven

H01L 2500

326 47, 326107, 257208, 257211, 438128, 438129

An integrated circuit includes a serpentine conductor track extending through a plurality of conductor layers and having ends coupled to first and second circuit elements, the ends being in opposing outermost ones of the conductor layers. The serpentine conductor track can selectively be made to be (i) continuous and electrically couple the first and second circuit elements together or (ii) discontinuous so that the first and second conductor elements are not electrically coupled. In the latter case, the discontinuity can be formed in any one of the conductor layers and a bridging conductor track is further formed in that one conductor layer which is coupled to the serpentine conductor track and which bypasses either of the first and second circuit elements. This structure has the advantage that circuit changes can be made in any conductor layer. It has particular utility in the implementation of module ID circuits, where it is desirable to change the output of a module ID circuit to reflect a circuit revision in the integrated circuit.

6529053, Mar 4, 2003

Apr 5, 2001

09/826570

Rune H. Jensen - San Francisco CA

Koninklijke Philips Electronics N.V. - Eindhoven

H03L 700

327142, 327141

The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset signal generator is coupled to a clock module having an external clock reference and to each of the peripheral devices. A reset clock signal having the reference clock frequency is sent to each of the peripheral devices via clock outputs at the clock module. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the clock signal. The clock module holds the reset clock signal for a selected amount of time, and then releases the signal from the external clock. The reset signals are then simultaneously released at each of the peripheral devices, making possible a smooth transition from reset.

6640310, Oct 28, 2003

Jun 20, 2002

10/176209

Rune Hartung Jensen - Sunnyvale CA
Thomas ODwyer - Sunnyvale CA
Michael Gartlan - Sunnyvale CA

Koninklijke Philips Electronics N.V. - Eindhoven

G06F 106

713500, 713400, 713600, 710 61, 710118, 709400

A clock module operates in conjunction with the generation of the bus-clock signal to provide a combination of module-clocks that can be relied upon to provide an adequate safety margin for data transfers among processing modules at the speed of the bus-clock. In a preferred embodiment, a system-clock generates the bus-clock and a sample-clock, the sample-clock having a predetermined phase relationship with respect to the bus-clock. Base-clocks at each of the frequencies required for each processing module are generated in the conventional manner, and, in accordance with this invention, are sampled by the sample-clock to produce sampled module-clocks that are provided to each corresponding processing module. By sampling each base-clock with a sample-clock that has a corresponding predetermined phase relationship with respect to the bus-clock, each module-clock will have a predetermined phase relationship with respect to the bus-clock. By selecting the predetermined phase relationship appropriately, an optimal data transfer speed can be achieved.