Russell W Dyer, 80333 Old Stage Rd, Cave Junction, OR 97523

6433785, Aug 13, 2002

Apr 9, 1999

09/288878

Serafin E. Garcia - Folsom CA
Russell W. Dyer - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 1316

345531, 345534, 345537, 710305

An embodiment of a memory controller that improves processor to graphics device throughput by reducing the frequency of retries of postable write transaction requests is disclosed. The memory controller includes a posted write buffer and a timeout counter. The memory controller is coupled to a processor via a host bus and is also coupled to a graphics device via a graphics bus. If the posted write buffer is unavailable when a first postable write transaction request is received by the memory controller, the memory controller stalls the host bus and waits for the posted write buffer to become available. If a second transaction request is received while the posted write buffers are unavailable, the timeout counter is initiated. If the posted write buffer becomes available before the timeout counter expires, the first postable write transaction request is completed. If, however, the timeout counter expires before the posted write buffer becomes available, the memory controller issues a retry response to the processor, indicating to the processor that the first postable write transaction request must be reissued at a later time.

6457121, Sep 24, 2002

Mar 17, 1999

09/270981

Altug Koker - Rancho Cordova CA
Russell W. Dyer - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 1200

712300, 345656, 345537

A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.

6505259, Jan 7, 2003

Aug 27, 1999

09/384128

Serafin E. Garcia - Folsom CA
Russell W. Dyer - El Dorado Hills CA
Abdul H. Pasha - Orangevale CA

Intel Corporation - Santa Clara CA

G06F 1300

710 35, 710 20, 710 52, 711169

A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

6593931, Jul 15, 2003

Dec 1, 1999

09/452540

Josh B. Mastronarde - Sacremento CA
Russell W. Dyer - El Dorado Hills CA
Himanshu Sinha - Citrus Heights CA

Intel Corporation - Santa Clara CA

G06F 1318

345535, 345557, 345568, 711205, 711206, 711207

An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

6629220, Sep 30, 2003

Aug 20, 1999

09/372147

Russell W. Dyer - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 1200

711158, 711151, 711105, 711163, 710240, 710244, 710220

Dynamic arbitration based on a high priority transaction type. A first memory access request is received at a first request queue. If the first memory access request is of a first type, the priority of the first request queue is dynamically raised over the priority of a second request queue. The priority of the second request queue is dynamically raised over that of the first request queue when requests of the first type in the first request queue, up to a maximum predetermined number of requests, have been serviced.

6665794, Dec 16, 2003

Sep 24, 2002

10/254146

Altug Koker - Rancho Cordova CA
Russell W. Dyer - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 500

712300, 345520

A device to change the ordering of datums in a packet from a storage device to a pre-determined ordering according to their addresses. The device has a first circuit to receive and process address information to determine a data ordering of data associated with the address information; and a second circuit to reorder the data into ordered packets in the predetermined ordering. This device can be used to efficiently transfer graphic data through the AGP bus in a computer.

7058736, Jun 6, 2006

Nov 11, 2002

10/292031

Serafin E. Garcia - Folsom CA, US
Russell W. Dyer - El Dorado Hills CA, US
Abdul H. Pasha - Orangevale CA, US

Intel Corporation - Santa Clara CA

G06F 13/00

710 35, 710 20, 710 52, 710 66, 711169

A method includes reordering a non-linear burst transaction initiated by a processor targeting a peripheral bus to a linear order, and retrieving the linear burst from the peripheral bus.

7089367, Aug 8, 2006

Aug 11, 1999

09/372296

Altug Koker - Rancho Cordova CA, US
Russell W. Dyer - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06F 12/00

711137, 711154, 711133, 711159, 707204

The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a plurality of data from the memory to a cache queue in response to a request. The cache controller is coupled to the cache queue and the pre-fetcher to deliver the pre-fetched data from the cache queue to the bus in a pipeline chain independently of the memory.