Charles Patrick Ryan, 61Scottsdale, AZ

6363474, Mar 26, 2002

Jun 30, 1999

09/345229

Lowell McCulley - Phoenix AZ
Charles Ryan - Phoenix AZ
Ronald Yoder - Mesa AZ

Bull HN Information Systems Inc. - Billerica MA

G06F 1202

712202, 712228, 712227, 712225, 712248, 712216, 711132

In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be performed in fewer cycles by utilizing a plurality of sets of registers maintained in a round-robin system. Whenever a transition is made to a higher security environment, a switch is made to a different set of registers. Then, when a transition is made back to the lower security environment, a switch is made back to the previous set of registers. Writes to memory copies of registers are detected, and only those registers whose memory copies have been modified are restored from the memory copy.

6442681, Aug 27, 2002

Dec 28, 1998

09/221392

Charles P. Ryan - Phoenix AZ
Patrice Brossard - Boulogne, FR

Bull HN Information Systems Inc. - Billerica MA

G06F 1200

712238, 712233, 712237, 711140, 711125, 711169

A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes an instruction buffer adjunct for storing an information set for each sub-block resident in the instruction buffers. A branch cache directory stores instruction buffer addresses corresponding to current entries in the instruction buffer adjunct, and a target address RAM stores target addresses developed from prior searches of the branch cache. A delay pipe is used to selectively step an information set read from the buffer instruction adjunct in synchronism with a transfer instruction traversing the pipeline. A comparison, at a predetermined phase along the delay pipe, determines if the information set identifies, as currently resident in the instruction buffers, a target address that matches the target address in the transfer instruction traversing the pipeline. If there is a finding that the information set traversing the delay pipe identifies a target address in the instruction buffers that matches the target address in the transfer instruction traversing the pipeline and there is an indication of TRA-GO from the pipeline, the instruction identified by the target address is sent to the pipeline from the instruction buffers rather than from the instruction cache.

6530076, Mar 4, 2003

Dec 23, 1999

09/472114

Charles P. Ryan - Phoenix AZ
Ron Yoder - Mesa AZ
William A. Shelly - Phoenix AZ

Bull HN Information Systems Inc. - Billerica MA

G06F 944

717128, 717124, 712227, 714 38, 714 45

A processor ( ) contains a Trace RAM ( ) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cache controller ( ) and the arithmetic (AX) processor ( ). A second trace mode selectively traces full operand words that result from microcode instruction ( ). Each microcode instruction word ( ) has a trace enable bit ( ) that when enabled causes the results of that microcode instruction ( ) to be recorded in the Trace RAM ( ).

6604060, Aug 5, 2003

Jun 29, 2000

09/607023

Charles P. Ryan - Phoenix AZ
Eric E. Conway - Mesa AZ

Bull HN Information Systems Inc. - Billerica MA

G06F 1130

702186, 709224, 714 12

In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors ( ) sharing an L2 cache ( ) differs from the time it takes for those signals to travel between processors ( ) not sharing the same L2 cache ( ). This difference, or DELTA, is dynamically computed by computing ( ) the time it takes for a invalidate cache line cache command to travel between a local processor ( ) and a master processor ( ). This computation ( ) is then made for the time it takes the signal to travel between a remote processor ( ) and the master processor ( ). The difference ( ) is the DELTA value in cycles. This DELTA value can then be utilized to bias delay values when exhaustively testing the interactions among multiple processors in a CC-NUMA environment ( ).

6760811, Jul 6, 2004

Aug 15, 2002

10/219644

Wayne R. Buzby - Phoenix AZ
Charles P. Ryan - Phoenix AZ

Bull HN Information Systems Inc. - Billerica MA

G06F 1200

711130, 711118, 711119, 711120, 711121, 711122, 711147

In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches with the first and second private caches being coupled to the first shared cache, and the third and fourth private caches being coupled to the second shared cache, gateword hogging is prevented by providing a gate control flag in each processor. Priority is established for a processor to next acquire ownership of the gate control word by: broadcasting a âset gate control flagâ command to all processors such that setting the gate control flags establishes delays during which ownership of the gate control word will not be requested by another processor for predetermined periods established in each processor. Optionally, the processor so acquiring ownership broadcasts a âreset gate control flagâ command to all processors when it has acquired ownership of the gate control word.

6868483, Mar 15, 2005

Sep 26, 2002

10/256289

Wayne R. Buzby - Phoenix AZ, US
Charles P. Ryan - Phoenix AZ, US

Bull HN Information Systems Inc. - Billerica MA

G06F012/00

711121, 711130, 711135, 711138, 711141, 711142, 711143, 711147, 711118, 711152

In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and second private caches being coupled to the first shared cache and to one another via a first internal bus, and the third and fourth private caches being coupled to the second shared cache and to one another via a second internal bus; method and apparatus for preventing hogging of ownership of a gateword stored in the main memory and which governs access to common code/data shared by processes running in at least three of the processors. Each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use.

6898738, May 24, 2005

Jul 17, 2001

09/907302

Charles P. Ryan - Phoenix AZ, US
William A. Shelly - Phoenix AZ, US
Stephen A. Schuerich - Phoenix AZ, US

Bull HN Information Systems Inc. - Billerica MA

G06F011/00

714 42, 714 5, 714 49, 714 54

Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to the search value. At the same time, they are also parity checked and compared against each other. If a match is made on either the primary entry or the duplicate entry, and that entry does not have a parity error, a cache “hit” is indicated. All single bit cache tag parity errors are detected and compensated for. Almost all multiple bit cache tag parity errors are detected.

6970977, Nov 29, 2005

Mar 31, 2003

10/403703

Wayne R. Buzby - Phoenix AZ, US
Charles P. Ryan - Phoenix AZ, US
Robert J. Baryla - Phoenix AZ, US
William A. Shelly - Phoenix AZ, US
Lowell D. McCulley - Phoenix AZ, US

Bull HN Information Systems Inc. - Billerica MA

G06F012/00

711130, 711122, 711135

In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cache; method and apparatus for preventing hogging of ownership of a gateword stored in the memory which governs access to common code/data shared by processes running in the processors by which a read copy of the gateword is obtained by a given processor by performing successive swap operations between the memory and the given processor's shared cache, and the given processor's shared cache and private cache. If the gateword is found to be OPEN, it is CLOSEd by the given processor, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword CLOSEd in memory such that the given processor obtains exclusive access to the governed common code/data. When the given processor completes use of the common code/data, it writes the gateword OPEN in its private cache, and successive swap operations are performed between the given processor's private cache and shared cache and shared cache and memory to write the gateword OPEN in memory.