Sabina Joseph, 50Fort Worth, TX

2004023, Nov 18, 2004

May 12, 2003

10/435973

Bodo Hoppe - Tam, DE
Sabina Joseph - Poughkeepsie NY, US
Haresh Kumar - Poughkeepsie NY, US
Jose Silverio - Danbury CT, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F017/50

703/014000

The complexity of present ASIC designs has increased considerably with the integration of multiple asynchronous frequency clock domains. The verification of these hardware models before actual tape out has become more and more important. A system and method are described herein to perform asynchronous stress testing using a single cycle random simulation environment. The system and method both include three phases. First, the domain frequency values are manipulated and a greatest common factor (GCF) mathematical approach is used to calculate a common unit of time. Secondly, corresponding default simulation cycles per system clock for each domain are calculated using the common unit of time determined from the previous phase. Lastly, a stress test is performed by randomly selecting a specific range above and below the default simulation cycle value for each clock domain. The method can be integrated as part of the single cycle random simulation environment, thus becoming added feature to an existing environment which is used for all functional verification. In addition, the method is used early in the design verification cycle before tape out, thus providing considerable cost savings in the event of hardware bugs.