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Sachin S Deo, 529101 La Cresada Dr APT 3122, Austin, TX 78749

Sachin Deo Phones & Addresses

9101 La Cresada Dr APT 3122, Austin, TX 78749    512-2913438   

5800 Brodie St, Austin, TX 78745    512-8926742   

6201 Sneed Cv, Austin, TX 78744    512-4620249   

Burney, IN   

5800 Brodie Ln APT 422, Austin, TX 78745    512-6996752   

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Sachin S Deo

Sachin Deo resumes & CV records

Resumes

Sachin Deo Photo 28

Staff Engineer

Location:
305 Interlocken Pkwy, Broomfield, CO 80021
Industry:
Semiconductors
Work:
Tensilica Feb 2006 - Nov 2008
Senior Engineer, Dsp Firmware
Sasken Mar 2005 - Jan 2006
Project Lead
Cirrus Logic Feb 1997 - Feb 2005
Staff Engineer, Direct Support Professional Firmware
Technofour Industries Jun 1992 - Jul 1993
Electronics Engineer
Dsp Firmware Jun 1992 - Jul 1993
Staff Engineer
Education:
Indian Institute of Science (Iisc) 1995 - 1997
Masters, Master of Engineering, Communication, Engineering
Maharashtra Academy of Engineering and Educational Research Maharashtra Institute of Technology, Kothrud, Pune 38 1988 - 1992
Bachelor of Engineering, Bachelors, Electronics
Skills:
Digital Signal Processors, Embedded Systems, Semiconductors, Processors, Soc, Firmware, Embedded Software, Electronics, Debugging, Rtos, Fpga, Digital Signal Processing, C
Sachin Deo Photo 29

Sachin Deo

Sachin Deo Photo 30

Sachin Denver Deo

Sachin Deo Photo 31

Sachin Deo

Publications & IP owners

Us Patents

Systems And Methods For Decoding Compressed Data

US Patent:
6504496, Jan 7, 2003
Filed:
Apr 10, 2001
Appl. No.:
09/832290
Inventors:
Vladimir Mesarovic - Austin TX
Raghunath Krishna Rao - Austin TX
Miroslav Dokic - Austin TX
Sachin Sunil Deo - Austin TX
Nariankadu Datareya Hemkumar - Rochester MN
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 700
US Classification:
341106, 341 51
Abstract:
A method of decoding an encoded bitstream. The method includes performing a two-table lookup. A first table is addressed in response to a first plurality of bits from the bitstream. An address into a second table is generated using a value in an entry in said first table accessed in the addressing step. A value (representing the decoded value corresponding to the codeword in the bitstream) in an entry in said second table at the address from the generating step is output.

Multi-Chip Camera Controller System With Inter-Chip Communication

US Patent:
2022032, Oct 13, 2022
Filed:
May 5, 2022
Appl. No.:
17/737615
Inventors:
- Edinburgh, GB
Nariankadu D. Hemkumar - Austin TX, US
Sachin Deo - Austin TX, US
Daniel T. Bogard - Austin TX, US
Nathan Daniel Pozniak Buchanan - Austin TX, US
Eric B. Smith - Austin TX, US
International Classification:
H04N 5/232
Abstract:
A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the secondary camera controller device. The primary camera controller device processes the received sensor data and the received position information to generate control data, sends a secondary portion of the control data to the secondary camera controller device via the communication link, and drives a primary portion of the control data to the actuators. The secondary camera controller device drives the received secondary portion of the control data to the actuators concurrently with the primary camera controller device driving the primary portion of the control data to the actuators.

Multi-Chip Camera Controller System With Inter-Chip Communication

US Patent:
2022032, Oct 6, 2022
Filed:
May 5, 2022
Appl. No.:
17/737673
Inventors:
- Edinburgh, GB
Nariankadu D. Hemkumar - Austin TX, US
Sachin Deo - Austin TX, US
Daniel T. Bogard - Austin TX, US
Nathan Daniel Pozniak Buchanan - Austin TX, US
Eric B. Smith - Austin TX, US
International Classification:
H04N 5/232
G01D 5/14
G03B 13/36
Abstract:
A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.

Flexible Latency-Minimized Delivery And Management Of Disparate-Rate Data Streams And Sub-Streams For Processing

US Patent:
2021002, Jan 28, 2021
Filed:
Jul 25, 2019
Appl. No.:
16/522580
Inventors:
- Edinburgh, GB
Nariankadu D. HEMKUMAR - Austin TX, US
Sachin DEO - Austin TX, US
Younes DJADI - Austin TX, US
Assignee:
Cirrus Logic International Semiconductor Ltd. - Edinburgh
International Classification:
H04N 5/378
H04N 5/374
H04N 5/3745
H04N 19/146
H04N 19/184
H04N 19/132
Abstract:
A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

Discrete Exchange And Update Of Multiple Consistent Subset Views Of An Evolving Data Store

US Patent:
2020039, Dec 17, 2020
Filed:
Jun 11, 2019
Appl. No.:
16/437746
Inventors:
- Edinburgh, GB
Roshan KAMATH - Austin TX, US
Nariankadu D. HEMKUMAR - Austin TX, US
Younes DJADI - Austin TX, US
Sachin DEO - Austin TX, US
Eric B. SMITH - Austin TX, US
Assignee:
Cirrus Logic International Semiconductor Ltd. - Edinburgh
International Classification:
G06F 3/06
H04N 5/232
Abstract:
A system for reading a plurality of subset views of an evolving data store may include for each subset view, a plurality of memory buffers comprising at least three buffers. The system may also include control circuitry for controlling the plurality of memory buffers of the plurality of subset views, the control circuitry configured to maintain, for each subset view, a variable defining a most-recently updated buffer of the plurality of buffers such that a read request for such subset view will respond with data of the most-recently updated buffer of such subset view; and responsive to an update of data of the evolving data store (i): determine, for each subset view, a selected data buffer of the plurality of buffers other than the most-recently updated buffer for such subset view to write updated subset view information; (ii) cause, for each subset view, the updated subset view information for such subset view to be written to the selected data buffer for such subset view; and (iii) substantially simultaneously across all of the plurality of subset views, update the variables defining the most-recently updated buffer of the plurality of subset views such that a subsequent read request for a subset view will respond with the updated subset view information for such subset view.

Flexible, Non-Blocking Asynchronous Transfer Of Time-Variant Atomic Data

US Patent:
2020035, Nov 12, 2020
Filed:
May 6, 2019
Appl. No.:
16/404323
Inventors:
- Edinburgh, GB
Nariankadu D. HEMKUMAR - Austin TX, US
Sachin DEO - Austin TX, US
Assignee:
Cirrus Logic International Semiconductor Ltd. - Edinburgh
International Classification:
G06F 12/0806
H04N 5/232
Abstract:
A system for atomically transferring vectors of data from a transmitter of the vectors of data to a receiver of the vectors of data may include a plurality of memory buffers configured to store the vectors of the data, each buffer configured to store one vector of the vectors of data at a time, the plurality of memory buffers comprising at least three memory buffers and a controller for controlling the plurality of memory buffers. The controller may be configured to, responsive to a condition for transferring information represented by the vectors of data to the receiver, determine which of the plurality of buffers from which the receiver may receive most-recently updated information completely written to the plurality of buffers by the transmitter. The controller may further be configured to, responsive to a condition for updating information represented by the vectors of data, determine which of the plurality of buffers for the transmitter to write updated information without blocking atomic receipt by the receiver of information from a most-recently updated buffer.

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