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Sachin A Joshi, 5121770 Poole Ct, Broadlands, VA 20148

Related to:
Rashmi S Joshi 50 Yash Joshi 24

Sachin Joshi Phones & Addresses

42618 Beckett Ter, Ashburn, VA 20148   

Broadlands, VA   

Cupertino, CA   

Sunnyvale, CA   

1055 Manet Dr APT 2, Sunnyvale, CA 94087   

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Sachin Joshi resumes & CV records

Resumes

Sachin Joshi Photo 38

Sachin V Joshi

Sachin Joshi Photo 39

Sachin Joshi

Location:
United States
Sachin Joshi Photo 40

Sachin Joshi

Location:
United States
Sachin Joshi Photo 41

Sachin Joshi

Location:
United States
Sachin Joshi Photo 42

Sachin Joshi

Location:
Pune, Maharashtra, India
Industry:
Computer Software
Work:
infosys May 2006 - Feb 2008
Programmer Analyst VisualSoft Jun 2003 - Apr 2005
Senior Software Engineer
Education:
Doctor Babasaheb Ambedkar Marathwada University 1996 - 2000
BE, Indtrumentation
Sachin Joshi Photo 43

Sachin Joshi

Location:
United States
Sachin Joshi Photo 44

Sachin Joshi

Location:
United States

Publications & IP owners

Us Patents

Content Addressable Memory Having Programmable Interconnect Structure

US Patent:
7643353, Jan 5, 2010
Filed:
Jun 3, 2008
Appl. No.:
12/131992
Inventors:
Maheshwaran Srinivasan - Sunnyvale CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Sandeep Khanna - Los Altos CA, US
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G11C 7/00
US Classification:
36518902, 365 491
Abstract:
A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and is configured to selectively route the match results from a first CAM row as an input match signal to any number of arbitrarily selected CAM rows at the same time.

Regular Expression Search Engine

US Patent:
7656716, Feb 2, 2010
Filed:
Dec 22, 2008
Appl. No.:
12/341284
Inventors:
Varadarajan Srinivasan - Los Altos Hills CA, US
Maheshwaran Srinivasan - Santa Clara CA, US
Sachin Joshi - Fremont CA, US
Sandeep Khanna - Los Altos CA, US
De Cai Li - Fremont CA, US
Assignee:
NetLogic Microsystems, Inc - Mountain View CA
International Classification:
G11C 7/00
US Classification:
36518902, 365 491
Abstract:
A system for searching an input string for a number of regular expressions includes a search block and a compiler. The search block includes a plurality of content addressable memory (CAM) devices, wherein each of the CAM devices is differently configured to implement search operations for regular expressions having a unique level of complexity. The compiler is configured to determine the complexity level of each of the regular expressions, and is configured to store each regular expression in a selected one of the CAM devices according to its complexity level.

Content Addresable Memory Having Selectively Interconnected Counter Circuits

US Patent:
7660140, Feb 9, 2010
Filed:
Dec 22, 2008
Appl. No.:
12/341754
Inventors:
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Maheshwaran Srinivasan - Santa Clara CA, US
Sandeep Khanna - Los Altos CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G11C 15/00
US Classification:
365 4917, 365 491
Abstract:
A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Content Addresable Memory Having Programmable Interconnect Structure

US Patent:
7821844, Oct 26, 2010
Filed:
Nov 12, 2009
Appl. No.:
12/617369
Inventors:
Maheshwaran Srinivasan - Sunnyvale CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Sandeep Khanna - Los Altos CA, US
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Assignee:
NetLogic Microsystems, Inc - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
36518902, 365 491
Abstract:
A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Content Addresable Memory Having Selectively Interconnected Counter Circuits

US Patent:
7826242, Nov 2, 2010
Filed:
Nov 16, 2009
Appl. No.:
12/619607
Inventors:
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Maheshwaran Srinivasan - Santa Clara CA, US
Sandeep Khanna - Los Altos CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 15/00
US Classification:
365 4917, 365 491
Abstract:
A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Content Addressable Memory Having Selectively Interconnected Rows Of Counter Circuits

US Patent:
7876590, Jan 25, 2011
Filed:
Aug 31, 2010
Appl. No.:
12/873183
Inventors:
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Maheshwaran Srinivasan - Santa Clara CA, US
Sandeep Khanna - Los Altos CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 15/00
US Classification:
365 4917, 365 491
Abstract:
A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Power Reduction In A Content Addressable Memory Having Programmable Interconnect Structure

US Patent:
7881125, Feb 1, 2011
Filed:
Aug 31, 2010
Appl. No.:
12/873122
Inventors:
Maheshwaran Srinivasan - Sunnyvale CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Sandeep Khanna - Los Altos CA, US
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 7/00
US Classification:
36518902, 365 491
Abstract:
A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Reformulating Regular Expressions Into Architecture-Dependent Bit Groups

US Patent:
7916510, Mar 29, 2011
Filed:
Jul 27, 2010
Appl. No.:
12/844321
Inventors:
Alexei Starovoitov - Los Gatos CA, US
Maheshwaran Srinivasan - Sunnyvale CA, US
Varadarajan Srinivasan - Los Altos Hills CA, US
Sandeep Khanna - Los Altos CA, US
Sachin Joshi - Fremont CA, US
Mark Birman - Los Altos CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
G11C 15/00
US Classification:
365 491, 365 4917
Abstract:
An apparatus and method of programming a search engine to implement regular expression search operations are disclosed that selectively transform a source regular expression into an equivalent reformulated regular expression in response to a determination of the architectural characteristics of the search engine. In this manner, the regular expression can be reformulated to optimize the configuration and available resources of the associated search engine.

Possible Relatives

Daisy C Joshi  Deepa Joshi  Deval D Joshi  Devang Joshi  Deven Joshi  Devendra Joshi  Dhananjay A Joshi  Sachin S Singh  Sachin R Patel  Sachin Prasad 

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