Salim U Chowdhury, 7013512 Utah Flats Dr, Austin, TX 78727

7454730, Nov 18, 2008

Dec 2, 2005

11/293058

Salim U. Chowdhury - Austin TX, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 17/50

716 6

A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.

7949976, May 24, 2011

May 23, 2008

12/125945

Jingyan Zuo - San Jose CA, US
Yu-Yen Mo - San Jose CA, US
Salim Chowdhury - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 17/50
G06F 9/455

716113, 716101, 716106, 716108, 716111, 716134, 716136, 716139

An improved, systematic approach is provided for automatically determining which cells in a circuit should be replaced to satisfy timing adjustment requirements (TAR's), and automatically replacing the cells with replacement cells to meet the TAR's. With the improved approach, there is a high likelihood that an optimal replacement scheme will be found which requires the fewest number of cells to be replaced while still satisfying all of the TAR's.

8176459, May 8, 2012

Dec 10, 2008

12/332013

Salim U. Chowdhury - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 9/455
G06F 17/50

716133, 716106, 716108, 716109, 716132, 716135

For each of a plurality of interconnected gates forming one or more non-critical timing paths through a logic block, a gate size may be selected based on (i) a gate delay, (ii) a change in gate delay and gate power associated with downsizing the gate to a next available gate size, and (iii) signal arrival times at one or more inputs and outputs of the gate to minimize power consumed by the logic block while maintaining a specified cycle time.

8612917, Dec 17, 2013

May 7, 2009

12/437174

Salim U. Chowdhury - Austin TX, US

Oracle America, Inc. - Redwood City CA

G06F 17/50
G06F 9/455
G06F 11/22

716132, 716134, 716135, 716136

A method for selecting gate sizes for a logic network of an integrated circuit, wherein the logic network is defined by a plurality of logic paths that includes nodes, gates and interconnect, includes assigning, at one or more computers, gate sizes to gates adjacent to timing path end nodes of the logic network, determining an n-tuple of performance/loading parameters for each of the assigned gate sizes based on gate and interconnect delay models, and determining whether two or more logic paths share a descendent gate. Two or more logic paths that share a descendent gate are coupled. The method also includes grouping the n-tuples of parameters of coupled logic paths into bins based on gate sizes of the shared descendent gate, recursively propagating, node by node, the bins of n-tuples of parameters along the coupled logic paths, detecting whether any of the bins of n-tuples of parameters are suboptimal for all of the coupled logic paths based on a comparison of the n-tuples of parameters in bin-pairs, and eliminating all n-tuples of parameters of the suboptimal bins along the coupled logic paths to prune gate sizes associated with the suboptimal bins.

2012006, Mar 15, 2012

Sep 13, 2010

12/880275

Salim U. Chowdhury - Austin TX, US
Georgios Konstadinidis - San Jose CA, US

ORACLE INTERNATIONAL CORPORATION - Redwood City CA

G06F 17/50

716120, 716122

A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less than a predefined slack threshold. The at least one processing device may be further configured to, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The at least one processing device may still be further configured to swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold.

6493854, Dec 10, 2002

Oct 1, 1999

09/411725

Salim U. Chowdhury - Austin TX
David Ray Bearden - Austin TX

Motorola, Inc. - Schaumburg IL

G06F 1750

716 6, 716 2, 716 8, 716 10, 716 12, 716 18

A method of inserting repeaters into a network to improve timing characteristics of the network. Extraction and timing tools provide an RC network description and a slack report describing electrical and timing characteristics of a network. The timing characteristics include required arrival times of a signal generated at a source to each of the sinks of the network. A maximum slew rate is also defined at each of the sinks. Initial candidate locations for insertion of repeaters is determined. For a given set of legal repeater sizes, one or more sets of midvalue repeater sizes are determined which are used in successive approximation to identify actual repeater sizes to be considered at each of the candidate locations. At each candidate location, capacitance, required arrival time, and slew rate value (c, q, s) are determined in a bottom-up procedure. Suboptimal and invalid (c, q, s) choices at each candidate location are eliminated during successive iterations of the bottom-up procedure until the source node is reached.

2016009, Mar 31, 2016

Sep 30, 2014

14/502433

- Redwood City CA, US
Salim Chowdhury - Austin TX, US

G06F 17/50

Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit.