Sam S Liu, 5392-883 Welo St, Kapolei, HI 96707

7079717, Jul 18, 2006

Jan 28, 2004

10/766619

Sam Liu - Sunnyvale CA, US
Yan Wang - Sunnyvale CA, US

G02B 6/14
H04B 10/08
H04B 10/00
H03K 5/22
H03K 3/12

385 14, 398 22, 398133, 398134, 398135, 398136, 398137, 398138, 398139, 327 73, 327205

An On-Off control circuit between the IEEE1394a and IEEE1394b compliant physical layer (PHY) output driver circuitry and the glass fiber optical physical medium dependent (PMD) sub-layer within the architecture of the IEEE 1394b standard addresses the stability issue incurred by electronic circuit's inherent noise that interferes with the connection detecting procedure defined by the connection management protocol (CMP) of the IEEE 1394b standard. The circuit includes of a voltage divider to provide a reference voltage of about 50% of the output common mode voltage, a voltage comparator, and a feedback coupled to the positive input of the comparator to eliminate possible oscillation. The negative input of the comparator may be connected to the mid point of TPB termination network and the positive input of the comparator may be connected to the output of the voltage dividing circuit. The output of the comparator may be connected to the transmission enable bar input of the optical transceiver. In the process of connection detection, the common mode voltage of the TPB output toggles between 0 volt and 1. 5 volt.

7756348, Jul 13, 2010

Oct 30, 2006

11/589447

Debargha Mukherjee - San Jose CA, US
Sam Liu - Mountain View CA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06K 9/36
H04N 5/14
G06K 9/46

382236, 348699

In a method for decomposing a block of a video sequence frame, it is determined as to whether either or both of the dimensions of the block equals a predetermined minimum dimension. In response to either or both of the dimensions equaling the predetermined minimum dimension, a motion vector for the block is sent. In response to both of the dimensions exceeding the predetermined minimum dimension, a motion vector for the block is determined, the block is partitioned into two wedges, the block is divided into four N/2×N/2 sub-blocks, and these steps are repeated on each of the four N/2×N/2 sub-blocks until either or both of the dimensions equal the predetermined minimum dimension.

8068722, Nov 29, 2011

Oct 5, 2005

11/575194

Hiroshi Yahata - Osaka, JP
Tomoyuki Okada - Nara, JP
Sam Liu - Mountain View CA, US
Gabe B. Beged-Dov - Corvallis OR, US

Panasonic Corporation - Osaka
Hewlett-Packard Development Company L.P. - Houston TX

H04N 5/84

386334, 386248, 386338, 386356

The present invention provides an information storage medium in which a stream including basic data and extension data for next generation is stored, so as to allow a decoder capable of decoding only basic data to process such a stream including basic data and extension data. Such information storage medium is an information storage medium on which an audio stream including a plurality of TS packets is stored, wherein each of the TS packets includes one of (a) a first packet including basic data, and (b) a second packet including extension data related to the basic data, the basic data is data capable of being decoded into complete sound without requiring the extension data, and the extension data is data intended for improving the quality of audio generated from the basic data, and a header of each of the TS packets includes an identifier indicating whether the TS packet includes the first packet or the second packet.

8392745, Mar 5, 2013

Apr 26, 2010

12/767226

Greg Goodemote - Tustin CA, US
Khan Kibria - Mission Viejo CA, US
Mark N. Fullerton - Austin TX, US
Niray P. Dagli - Placentia CA, US
Liang Deng - Sunnyvale CA, US
Sam Liu - Irvine CA, US

Broadcom Corporation - Irvine CA

G06F 1/00

713501, 713300, 713320, 713322

A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

8514938, Aug 20, 2013

Oct 5, 2005

11/576085

Tadamasa Toma - Osaka, JP
Tomoyuki Okada - Nara, JP
Sam Liu - Mountain View CA, US

Hewlett-Packard Development Company L.P. - Houston TX
Panasonic Corporation - Osaka

H04N 11/02

37524015, 37524025, 37524026

A picture coding apparatus reduces a load in decoding. The picture coding apparatus codes each picture according to a picture type of the picture. The picture types include at least an I picture, a P picture, a B picture, and a skipped picture. A first coder is configured to code first supplementary information, including coded pictures and indicating respective picture types of the coded pictures, in a decoding order of the coded pictures. A second coder is configured to code second supplementary information, indicating respective pieces of picture structure information of the coded pictures, in the decoding order. A writer is configured to write, at a position prior to a starting picture, the first supplementary information coded by said first coder and the second supplementary information coded by said second coder.

2006010, May 18, 2006

Nov 12, 2004

10/987863

Sam Liu - Mountain View CA, US

H04N 11/04
H04N 11/02
H04B 1/66
H04N 7/12

375240030, 375240160

A video bit stream having a constant frame rate is generated from an input having a frame rate that is different than the constant frame rate. Zero-motion difference frames are added to the bit stream to achieve the constant frame rate. Bit rate control may include using a state transition model to determine a noise masking factor for the frame; and assigning a number of bits as a function of the noise masking factor.

2007028, Dec 6, 2007

May 31, 2007

11/806397

Sam H. Liu - Irvine CA, US
Zhiqing Zhuang - Irvine CA, US
Chaoyang Zhao - Irvine CA, US
Vinay Bhasin - Irvine CA, US
Chenmin Zhang - Irvine CA, US
Lawrence J. Madar - San Francisco CA, US
Vafa J. Rakshani - Newport Coast CA, US

Broadcom Corporation - Irvine CA

H04L 7/00

375372

Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.

2008002, Jan 31, 2008

Jul 31, 2006

11/496806

Sam Liu - Palo Alto CA, US
Debargha Mukherjee - Palo Alto CA, US

H04N 11/02
H04N 7/12

37524025, 37524026

One embodiment in accordance with the invention is a method that can include determining a constraint that is associated with a decoder. Furthermore, the method can include determining a maximum number of reference B-frames that can be utilized to encode video content. Note that the maximum number is based on the constraint that is associated with the decoder.