Sam H Moy, 67417 Green Hills Dr, Millbrae, CA 94030

8335884, Dec 18, 2012

Jul 10, 2009

12/501389

Mehrdad Hamadani - San Jose CA, US
Deepak Bansal - San Jose CA, US
Sam Htin Moy - Daly City CA, US
Sreenivasulu Malli - Fremont CA, US
David Cheung - Cupertino CA, US
Mani Kancherla - Milpitas CA, US
Sridhar Devarapalli - Santa Clara CA, US

Brocade Communications Systems, Inc. - San Jose CA

G06F 13/00

710316, 710317

A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.

2010032, Dec 23, 2010

Jun 22, 2009

12/489366

Avinash Jindal - Milpitas CA, US
Deepak Bansal - San Jose CA, US
Sam Htin Moy - Daly City CA, US
David Cheung - Cupertino CA, US
Bing Wang - San Jose CA, US
Mani Kancherla - Milpitas CA, US
Sridhar Devarapalli - Santa Clara CA, US

Brocade Communications Systems, Inc. - San Jose CA

G06F 15/173
G06F 9/46

709226, 718105

A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.

5399995, Mar 21, 1995

Apr 8, 1994

8/225126

Jaime E. Kardontchik - Sunnyvale CA
Sam H. Moy - San Bruno CA

Raytheon Company - Lexington MA

H03L 700

331 17

A high speed clock recovery system that provides a precise 90. degree. phase shift at the incoming NRZ data rate by using a series of differential inverters and controlling their delays in accordance with the corresponding delays of differential inverters of a ring oscillator that is part of a phase-locked loop. More particularly, the incoming NRZ data and the phase shifted data are fed to an exclusive OR that provides an output signal including a frequency component of the originating clock of the NRZ data. The phase-locked loop further includes a phase detector which is responsive to the output of the exclusive OR and the ring oscillator. Thus, once the loop locks, the ring oscillator is synchronized to the frequency of the originating clock for the NRZ data. By slaving the differential inverters of the phase shifter and the ring oscillator to the same delays, the phase shifter provides a dynamically adjusted delay of precisely 90. degree. at the originating clock frequency of the incoming NRZ data.

5566204, Oct 15, 1996

May 2, 1994

8/236939

Jaime E. Kardontchik - Sunnyvale CA
Sam H. Moy - San Bruno CA
Jack P. Guedj - Los Altos CA

Raytheon Company - Lexington MA

H04B 138

375219

A transceiver integrated circuit including a transmitter section having a phase-locked loop with an oscillator to provide an output at a predetermined transmission frequency, and a receiver section having a phase-locked loop with an oscillator used to provide a recovered clock from an incoming data signal. In a second mode when no incoming data is being received, the receiver oscillator is controlled in accordance with the transmitter oscillator to operate the receiver oscillator at the expected frequency of future data. Therefore, when data is received, the receiver oscillator is at the same approximate frequency as the incoming data thereby enabling fast acquisition by merely adjusting the phase of the receiver oscillator to the incoming data. In particular, the receiver and transmitter oscillators are identical current controlled oscillators that are operated in the second mode at the same approximate frequency by feeding the receiver oscillator with a current that is substantially equal to the loop current controlling the transmitter oscillator. Further, to provide higher slaving accuracy, a frequency detector is used to compare the outputs of the receiver and transmitter oscillators in the second mode, and to control the receiver oscillator into frequency synchronism with the transmitter oscillator.

2017034, Nov 30, 2017

May 26, 2017

15/607030

- San Jose CA, US
Sam Moy - Millbrae CA, US
David Wang - San Jose CA, US
Sanjeev Chhabria - Castro Valley CA, US
Suneetha Sarala - Fremont CA, US

H04L 29/06
H04L 29/12

Techniques for implementing intelligent hardware assisted ICMP request processing in a network device are provided. According to one embodiment, the network device can receive an ICMP request packet and write the packet to a protocol buffer configured to queue packets for processing by a management CPU. When the ICMP request packet is ready to be processed by the management CPU, a hardware-based ICMP request handler of the network device can determine whether the ICMP request packet matches any entries in an ICMP table. If the ICMP request packet does match an entry in the ICMP table, the ICMP request handler can generate an ICMP response packet for replying to the ICMP request packet, without sending the ICMP request packet to the management CPU.

2014029, Oct 2, 2014

Feb 26, 2014

14/191007

- San Jose CA, US
Sam Moy - San Jose CA, US
Venkata Nambula - San Jose CA, US

Brocade Communications Systems, Inc. - San Jose CA

H04L 12/26
H04L 12/835

709224

Techniques for implementing application traffic prioritization in a network device are provided. In one embodiment, the network device can determine a packet buffer threshold for a received data packet. The network device can further compare the packet buffer threshold with a current usage of a packet buffer memory that stores data for data packets to be forwarded to a processing core of the network device. If the current usage of the packet buffer memory exceeds the packet buffer threshold, the network device can perform an action on the received data packet.