Sandeep Chaman Dhar, 64San Diego, CA

6868503, Mar 15, 2005

Jan 19, 2002

10/053226

Dragan Maksimovic - Boulder CO, US
Sandeep Dhar - Boulder CO, US
Bruno Kranzen - San Jose CA, US
Ravindra Ambatipudi - Milpitas CA, US

National Semiconductor Corporation - Santa Clara CA

G06F001/06

713401, 713400

There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

6985025, Jan 10, 2006

Jan 19, 2002

10/053858

Dragan Maksimovic - Boulder CO, US
Sandeep Dhar - Boulder CO, US

National Semiconductor Corporation - Santa Clara CA

G05F 1/10

327540, 327157

There is disclosed control circuitry for adjusting a power supply level, VDD, of a digital processing component having varying operating frequencies. The control circuitry comprises N delay cells and power supply adjustment circuitry. The N delay cells are coupled in series, each of which has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells. The power supply adjustment circuitry capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.

7024568, Apr 4, 2006

Sep 6, 2002

10/236482

Dragan Maksimovic - Boulder CO, US
Sandeep Dhar - Boulder CO, US

National Semiconductor Corporation - Santa Clara CA

G06F 1/26
H03H 11/26

713300, 327271, 327277

A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.

7061292, Jun 13, 2006

Nov 8, 2002

10/291098

Dragan Maksimovic - Boulder CO, US
Sandeep C. Dhar - Boulder CO, US

The Regents of the University of Colorado - Boulder CO

G05B 13/04
G05F 1/46
H03K 5/14

327277, 327161, 327540, 327544

Apparatus for efficiently supplying energy to a device in a circuit, the apparatus comprising a powered device having a critical path delay; delay line operative to model said critical path delay; control logic responsive to output from said delay line and operative to generate control output; and a power converter operative to adjust supply voltage to said powered device in response to said generated control output, wherein the delay line, the control logic, and the power converter cooperate to provide first order bang-bang control of said critical path delay.

7106040, Sep 12, 2006

Apr 14, 2003

10/414446

Dragan Maksimovic - Boulder CO, US
Sandeep Dhar - Boulder CO, US
Ravindra Ambatipudi - Milpitas CA, US
Bruno Kranzen - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

G05F 3/16

323314

There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.

7117378, Oct 3, 2006

Mar 14, 2005

11/079911

Dragan Maksimovic - Boulder CO, US
Sandeep Dhar - Boulder CO, US
Bruno Kranzen - San Jose CA, US
Ravindra Ambatipudi - Milpitas CA, US

National Semiconductor Corporation - Santa Clara CA

G06F 1/26
G06F 1/32
G06F 1/12

713300, 713320, 713401

There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

7581120, Aug 25, 2009

May 23, 2005

11/134997

Mark Hartman - Santa Clara CA, US
James T. Doyle - Nederland CO, US
Dragan Maksimovic - Boulder CO, US
Pasi Salmi - Kemi, FI
Juha Pennanen - Oulu, FI
Sandeep Dhar - Boulder CO, US

National Semiconductor Corporation - Santa Clara CA

G06F 1/26

713300, 327158, 713320

A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.

7595686, Sep 29, 2009

Dec 9, 2002

10/498337

Dragan Maksimovic - Boulder CO, US
Benjamin James Patella - Fort Collins CO, US
Aleksandar Prodic - Toronto, CA
Sandeep Chaman Dhar - Boulder CO, US

The Regents of the University of Colorado - Boulder CO

G05F 1/10
H02M 3/335
H03K 5/14
H03K 7/08

327540, 327176, 327277, 341161, 363 2111

A voltage controller (), the controller comprising: a voltage comparator () operative to provide a digital error signal (); a compensator () operative to determine a digital control signal () based on said provided error signal; and a modulator () operative to provide a power control signal () based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.