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Sanjay K Bhardwaj, 61701 Bodega Ct, Fremont, CA 94539

Sanjay Bhardwaj Phones & Addresses

701 Bodega Ct, Fremont, CA 94539    510-6512755   

Maricopa, AZ   

Plano, TX   

Menomonee Falls, WI   

Austin, TX   

Hayward, CA   

Sunnyvale, CA   

Santa Clara, CA   

Boxborough, MA   

Pinedale, AZ   

Work

Address: 701 Bodega Ct, Fremont, CA 94539 Specialities: Intellectual Property - 100%

Education

School / High School: Concord Law School

Ranks

Licence: California - Active Date: 2008

Mentions for Sanjay K Bhardwaj

Career records & work history

Lawyers & Attorneys

Sanjay Bhardwaj Photo 1

Sanjay Bhardwaj, Fremont CA - Lawyer

Address:
701 Bodega Ct, Fremont, CA 94539
510-2078283 (Office)
Licenses:
California - Active 2008
Education:
Concord Law School
Specialties:
Intellectual Property - 100%
Sanjay Bhardwaj Photo 2

Sanjay Bhardwaj, Fremont CA - Lawyer

Address:
44663 Japala Pl, Fremont, CA 94539

Sanjay Bhardwaj resumes & CV records

Resumes

Sanjay Bhardwaj Photo 29

Principal Attorney, Patents, Ip And Family Law

Location:
44663 Japala Pl, Fremont, CA 94539
Industry:
Law Practice
Work:
Law Offices of Sanjay Bhardwaj
Principal Attorney, Patents, Ip and Family Law
Dell Mar 2011 - Feb 2014
Principal Engineer
Cisco Mar 2006 - Oct 2009
Hardware Engineer
Infineon Technologies Aug 2001 - Oct 2003
Principal Engineer
Education:
Concord Law School 2004 - 2008
Doctor of Jurisprudence, Doctorates, Law
Santa Clara University 2001 - 2003
Master of Business Administration, Masters, Finance
University of Massachusetts Amherst May 1987
Masters
University of Massachusetts Amherst 1985 - 1987
Master of Science, Masters, Computer Engineering
Indian Institute 1985
Bachelors
Indian Institute of Technology, Kanpur 1981 - 1985
Sawan Public School 1978 - 1981
Central School 1973 - 1978
Concord University
Skills:
Registered Patent Attorney
Interests:
Boating
Electronics
Outdoors
Investing
Sports
Languages:
English
Sanjay Bhardwaj Photo 30

Senior Program Manager And Account Manager

Location:
300 State St, Rochester, NY 14614
Industry:
Information Services
Work:
Impetus
Senior Program Manager and Account Manager
Dun & Bradstreet Jul 2005 - Oct 2011
Leader, Mis and Hosting Services
Livecapital Jan 2004 - Jun 2005
Director, Mis and Enterprise Services
Livecapital Jan 2002 - Dec 2003
Director, Engineering
Bea Systems Sep 1995 - Nov 2001
Managing Principal
Iis Infotech 1994 - 1995
Senior Software Engineer
Eclipse Systems Pvt. Ltd. Feb 1992 - Sep 1994
Senior Software Engineer
Education:
Faculty of Management Studies and Research, Aligarh Muslim University
Masters, Computer Science
Faculty of Management Studies and Research, Aligarh Muslim University
Bachelors, Bachelor of Science, Physics
Skills:
San
Sanjay Bhardwaj Photo 31

Sanjay Bhardwaj

Sanjay Bhardwaj Photo 32

Sanjay Kumar Bhardwa Sanjay Kumar Bhardwaj

Sanjay Bhardwaj Photo 33

Sanjay Bhardwaj

Location:
San Francisco Bay Area
Industry:
Computer Hardware

Publications & IP owners

Us Patents

Method And Apparatus For Data Alignment

US Patent:
6813734, Nov 2, 2004
Filed:
Jan 26, 2001
Appl. No.:
09/771173
Inventors:
Sanjay Bhardwaj - Fremont CA
Assignee:
Catamaran Communications Incorporated - Fremont CA
International Classification:
G06F 1100
US Classification:
714 48, 370366
Abstract:
A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, the number of unaligned data scenarios may be reduced through the use of data stream element mapping. A complex data stream may be mapped onto a simple data stream with only the addition of multiplexers and simple logic to the data aligner. The implementation in network protocol related hardware, where a data stream is encoded and decoded for error detection and correction, may lead to a faster and more efficient pipelined design of checkers and generators, thereby, making them more desirable for higher frequency and higher bandwidth designs.

Method And Apparatus For Byte Rotation

US Patent:
6965606, Nov 15, 2005
Filed:
Jan 26, 2001
Appl. No.:
09/771172
Inventors:
Sanjay Bhardwaj - Fremont CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
G01R031/08
US Classification:
370428, 710 65
Abstract:
A scheme is described for distributing data operations on an irregular data stream over multiple stages of a data aligner to generate a regular data stream having continuous filled byte positions. In one particular embodiment, data alignment may involve the prediction of a rotation amount for unaligned data bytes. The rotation amount is predicted one clock cycle before actual rotation of data bytes based on the current contents of a buffer. The one cycle look ahead enables a large portion of calculations to be performed in a previous clock cycle and, thereby, may facilitate a high frequency design for a data aligner.

Method And Apparatus For Adapting Mac And Network Processor Core To Packet Format Changes And For Mapping Rpr Architecture Over Spatial Reuse Architecture

US Patent:
7441039, Oct 21, 2008
Filed:
Dec 4, 2003
Appl. No.:
10/729335
Inventors:
Sanjay Bhardwaj - Fremont CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
G06F 15/16
US Classification:
709230, 709249
Abstract:
A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantially protocol-independent core portion that is insulated from protocol changes. Translation and/or adaptation mechanisms in the peripheral portion of the device allow the device to handle changes in data format and/or pipeline changes such as error protection without affecting the core portion of the device. A device and method are provided for inter-operating with both the Spatial Reuse Protocol (SRP) and the Resilient Packet Ring (RPR) architectures.

Method And Apparatus For Frame Delineation

US Patent:
7814376, Oct 12, 2010
Filed:
Mar 1, 2004
Appl. No.:
10/790981
Inventors:
Sanjay Bhardwaj - Fremont CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
G06F 11/00
US Classification:
714707, 714776
Abstract:
A frame delineation mechanism which alternately considers even and odd sync pattern position possibilities. With the addition of toggle logic, each of 66 possible states of even and odd alignment are exhausted in turn, odd, followed by even, followed by odd and so on, providing synchronization more quickly than known mechanisms. Additionally, faster convergence is reached due to the use of an exhaust register which keeps track of those alignment states that were tested but did not provide synchronization. Until synchronization is acquired, the states indicated in the exhaust register are ignored in further attempts to acquire synchronization.

Generating An Encapsulating Header Based On Encapsulated Information Provided At Protocol-Dependent Locations

US Patent:
7873045, Jan 18, 2011
Filed:
Sep 15, 2003
Appl. No.:
10/662583
Inventors:
Sanjay Bhardwaj - Fremont CA, US
Assignee:
Exar Corporation - Fremont CA
International Classification:
H04L 12/28
H04L 12/56
G06F 15/16
G06F 15/173
US Classification:
370392, 370394, 709238, 709246
Abstract:
An encapsulation packet is received as a sequence of parallel data segments. First information within the encapsulated packet is obtained based on second information indicative of a location of the first information within the encapsulated packet. The encapsulating header is modified based on the first information.

Virtual Concatenation Receiver Processing With Memory Addressing Scheme To Avoid Delays At Address Scatter Points

US Patent:
2005009, May 5, 2005
Filed:
Oct 30, 2003
Appl. No.:
10/697414
Inventors:
Sanjay Bhardwaj - Fremont CA, US
International Classification:
H04J003/00
US Classification:
370476000
Abstract:
In processing received virtual concatenation frames, the memory write address can be appropriately controlled to force bank switches where address scattering occurs. Arbitrary identifiers assigned to the arriving frames and the subcolumns thereof are used instead of H4 information to calculate the memory write addresses.

Thin Film Process Monitoring Techniques Using Acoustic Waves

US Patent:
5271274, Dec 21, 1993
Filed:
Aug 14, 1991
Appl. No.:
7/745005
Inventors:
B. T. Khuri-Yakub - Palo Alto CA
Sanjay Bhardwaj - Stanford CA
Krishna Saraswat - Cupertino CA
Assignee:
The Board of Trustees of the Leland Stanford Junior University - Stanford CA
International Classification:
G01N 2910
G01N 2924
US Classification:
73597
Abstract:
A system and method is disclosed for measuring thickness of at least one film on a substrate by propagating an acoustic wave through the film on a substrate such that echo waves are generated and received by a transducer. An output signal is generated and processed to give a thickness value. The thickness valve is obtained from the time lapse between the propagated wave and receipt of the echo wave; by the frequency domain of the echo wave; or the phase of the echo wave.

Method, Apparatus And System For Connected Automobiles

US Patent:
2015019, Jul 9, 2015
Filed:
Mar 14, 2015
Appl. No.:
14/658169
Inventors:
Sanjay Bhardwaj - Fremont CA, US
International Classification:
H04W 40/02
Abstract:
An integrated device for connected cars that provides a plurality of standard and new interfaces, which is implemented in flexible hardware to overcome the mismatch between an automobile lifetime and cellular and semiconductor technology development. By providing interfaces in one device, greater synergy of applications is possible. Integration of the on board diagnostics with the infotainment device is a function enabler for the automobile ecosystem. The present invention is open to integration with the car electronic driver assistance and evolving autonomous driver modules, providing additional economies of scale.

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