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Satwant Singh, 60Madera, CA

Known as:
Sawant Singh
Related to:
Karanjit Singh 49 Amrit Pal Singh 44

Satwant Singh Phones & Addresses

Madera, CA   

Chowchilla, CA   

Fremont, CA   

2 Clauss St, Carteret, NJ 07008    732-5410714   

South Ozone Park, NY   

Sacramento, CA   

Flushing, NY   

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Mentions for Satwant Singh

Career records & work history

Medicine Doctors

Satwant Singh

Specialties:
Nephrology, Internal Medicine
Work:
Dialysis Clinic Inc
499 E Mcmillan St STE 103, Cincinnati, OH 45206
513-2810091 (phone) 513-2213425 (fax)
Davita Dialysis Center
232 State Rd 129 S, Batesville, IN 47006
812-9345653 (phone) 812-9345657 (fax)
Davita Dialysis
2109 Reading Rd STE 2109, Cincinnati, OH 45202
513-7841800 (phone) 513-7232355 (fax)
UC Physicians Nephrologists
231 Albert Sabin Way, Cincinnati, OH 45267
513-5585471 (phone) 513-5584309 (fax)
Education:
Medical School
Gov't Med Coll, Guru Nanak Dev Univ, Amritsar, Punjab, India
Graduated: 1963
Procedures:
Cardiac Stress Test, Dialysis Procedures
Conditions:
Acute Myocardial Infarction (AMI), Acute Pancreatitis, Acute Renal Failure, Alcohol Dependence, Anemia, Arterial Thromboembolic Disease, Atrial Fibrillation and Atrial Flutter, Bacterial Pneumonia, Benign Prostatic Hypertrophy, Calculus of the Urinary System, Cardiac Arrhythmia, Cardiomyopathy, Chronic Bronchitis, Chronic Renal Disease, Cirrhosis, Dementia, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Endocarditis, Epilepsy, Fractures, Dislocations, Derangement, and Sprains, Gastrointestinal Hemorrhage, Heart Failure, Hemolytic Anemia, Hemorrhagic stroke, Herpes Zoster, HIV Infection, Hypertension (HTN), Ischemic Heart Disease, Multiple Sclerosis (MS), Myasthenia Gravis (MG), Nephrotic Syndrome, Osteomyelitis, Pericardidtis, Peripheral Nerve Disorders, Pneumonia, Poisoning by Drugs, Meds, or Biological Substances, Pulmonary Embolism, Septicemia, Sickle-Cell Disease, Skin and Subcutaneous Infections, Substance Abuse and/or Dependency, Systemic Lupus Erythematosus, Urinary Tract Infection (UT), Venous Embolism and Thrombosis
Languages:
English, Russian, Spanish
Description:
Dr. Singh graduated from the Gov't Med Coll, Guru Nanak Dev Univ, Amritsar, Punjab, India in 1963. He works in Cincinnati, OH and 3 other locations and specializes in Nephrology and Internal Medicine. Dr. Singh is affiliated with Christ Hospital, Good Samaritan Hospital and UC Medical Center.

Satwant Singh resumes & CV records

Resumes

Satwant Singh Photo 43

Satwant Singh

Satwant Singh Photo 44

Satwant Singh

Satwant Singh Photo 45

Satwant Singh

Location:
United States
Satwant Singh Photo 46

Satwant "Sid" Singh - Cypress, CA

Work:
Kofax Oct 2009 to 2000
Team Lead Kofax - Irvine, CA Oct 2005 to Oct 2009
Diamond Support Analyst Fidelity National Financial - Santa Ana, CA Apr 2004 to Oct 2005
Support Analyst ADP - Roseland, NJ Jul 2000 to Apr 2004
Senior Support Specialist ADP - La Palma, CA Aug 1997 to Apr 2004
Senior PC Coordinator The Insco-Dico Group - Irvine, CA Sep 1994 to Jun 1997
Systems Support Specialist
Education:
CSU Fullerton - Fullerton, CA 1991 to 1994
BA in Management Information Systems Cypress College - Cypress, CA 1991 to 1993
AA in Business

Publications & IP owners

Us Patents

Method And Apparatus For Automated System Level Testing

US Patent:
6625758, Sep 23, 2003
Filed:
Jun 26, 2000
Appl. No.:
09/604267
Inventors:
Satwant Singh - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H02H 305
US Classification:
714 25
Abstract:
A system-level (SLT) of a CPU device is performed in an automated test environment. Each device under test is automatically placed an SLT station and a test is performed at an initial operating speed. A CPU device which passes the test is then automatically removed and placed in a storage container based on that operating speed, also known as a rating (or rated) speed. If the device fails the test, however, then it remains in the test station and the operating speed of the station is adjusted until the device is able to pass the test. Once successful, the device is automatically removed and placed in a storage container based on the operating speed at which it finally was successful. A device which is unable to pass a system-level test at any speed is automatically removed and placed in a reject bin. This testing procedure is repeated for a number of devices without requiring manual intervention to place the device in the SLT station, adjust the test operating speed, or binning the CPU device according to its rated speed.

Device And Method With Generic Logic Blocks

US Patent:
6765408, Jul 20, 2004
Filed:
Apr 26, 2002
Appl. No.:
10/133106
Inventors:
Jason Cheng - Fremont CA
Cyrus Tsui - Los Altos Hills CA
Satwant Singh - Fremont CA
Albert Chen - Palo Alto CA
Ju Shen - Saratoga CA
Clement Lee - Portland OR
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19177
US Classification:
326 41, 326 47
Abstract:
A programmable device and method with generic logic blocks. Each generic logic block is configurable to perform product term logic functions and memory functions, such as RAM, dual-port RAM, ROM, CAM, FIFO and switch.

Dynamic Cross Point Switch With Shadow Memory Architecture

US Patent:
6861870, Mar 1, 2005
Filed:
Feb 19, 2003
Appl. No.:
10/370232
Inventors:
Jason Cheng - Fremont CA, US
Satwant Singh - Fremont CA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F007/38
US Classification:
326 41, 326 39, 326 40, 326 38, 365 49, 36523003, 36518912
Abstract:
The fuse points within a programmable AND array may be programmed with configuration signals to select for logical signals to form product term outputs in a logic mode. In a switch mode, a subset of these fuse points may be programmed with dynamically-created operating signals to form a cross point switch matrix.

Programmable And Fixed Logic Circuitry For High-Speed Interfaces

US Patent:
6894530, May 17, 2005
Filed:
Apr 28, 2003
Appl. No.:
10/425862
Inventors:
Allan T. Davidson - San Jose CA, US
Satwant Singh - Fremont CA, US
Shari L. Mann - Sandy UT, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/173
US Classification:
326 38, 326 41
Abstract:
Systems and methods are disclosed for programmable logic devices requiring a high-speed input/output interface. Hard-macro circuits that are configurable, scalable, and cascadable complement the input/output drivers and the programmable core logic of the programmable logic device. The hard-macro circuits are permanent, high-speed logic circuits that are optimized for the performance requirements of high-speed input/output interface standards. High-speed memory interfaces, clock and data recovery interface standards, source-synchronous interface standards, and system-synchronous interface standards may be supported by the hard-macro circuits.

Programmable Logic Device With Enhanced Wide Input Product Term Cascading

US Patent:
6903573, Jun 7, 2005
Filed:
Jul 14, 2003
Appl. No.:
10/619711
Inventors:
Jason Cheng - Fremont CA, US
Cyrus Tsui - Los Altos Hills CA, US
Satwant Singh - Fremont CA, US
Albert Chan - Palo Alto CA, US
Ju Shen - Saratoga CA, US
Clement Lee - Portland OR, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/177
US Classification:
326 41, 326 47
Abstract:
A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Scalable Device Architecture For High-Speed Interfaces

US Patent:
6903575, Jun 7, 2005
Filed:
Apr 28, 2003
Appl. No.:
10/425863
Inventors:
Allan T. Davidson - San Jose CA, US
Satwant Singh - Fremont CA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/173
H01L025/00
US Classification:
326 47, 326 41, 326 38
Abstract:
An architecture is disclosed to provide high-speed input/output interface capabilities for programmable devices. One or more configurable input/output circuits are situated between the input/output drivers and the programmable core circuitry of the programmable device. The input/output circuits are optimized for the high-speed requirements of the input/output interface standards, with each input/output circuit configurable to support numerous, different input/output interface standards. The programmable core circuitry may be utilized to support the lower-speed requirements of the input/output interface standards.

Macrocells Supporting A Carry Cascade

US Patent:
6915323, Jul 5, 2005
Filed:
Feb 13, 2003
Appl. No.:
10/368023
Inventors:
Jason Chang - Fremont CA, US
Satwant Singh - Fremont CA, US
Ju Shen - Saratoga CA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F007/50
US Classification:
708707
Abstract:
A programmable logic device includes a plurality of logic blocks. Each logic block includes a plurality of macrocells, with each macrocell being configurable to register a sum of product term output. In addition, the macrocells within each logic block are arranged from a first macrocell to a last macrocell. Each macrocell is associated with a carry-in and a carry-out signal. The macrocells are configured to support a carry cascade such that the carry-out signal from the first macrocell becomes the carry-in signal for the second macrocell, and so on.

Fifo Memory With Programmable Data Port Widths

US Patent:
6986004, Jan 10, 2006
Filed:
Apr 8, 2003
Appl. No.:
10/409543
Inventors:
Chan-Chi Jason Cheng - Fremont CA, US
Bradley Felton - Chippenham, GB
Satwant Singh - Fremont CA, US
Andrew Armitage - Chippenham, GB
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G06F 12/00
US Classification:
711149, 711101, 711212, 711154
Abstract:
A memory provides a programmable write port data width and an independently programmable read port data width. The independence between the programmable write port data width and the programmable read port data width is achieved without the use of a third clock domain.

Possible Relatives

David J Singh  Davinder Singh  Davinderpal Singh  Dawinder Singh  Dale D Singh  Daler Singh  Dalip D Singh  Satwant S Grewal  Satwant Sandhu  Satwant Kour 

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