Saurabh Sinha, 39San Antonio, TX

2022019, Jun 23, 2022

Jun 10, 2021

17/343829

- Cambridge, GB
Saurabh Pijuskumar Sinha - Schertz TX, US
Shidhartha Das - Upper Cambourne, GB
Mudit Bhargava - Austin TX, US
Rahul Mathur - Austin TX, US

G11C 5/14
G11C 5/02

Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

2023003, Feb 9, 2023

Aug 6, 2021

17/396452

- Cambridge, GB
Saurabh Pijuskumar Sinha - Schertz TX, US
Douglas James Joseph - Leander TX, US
Tiago Rogerio Muck - Austin TX, US

H04L 12/775
H04L 12/933
H04L 12/26
G06F 15/78

Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.

2021038, Dec 16, 2021

Oct 23, 2019

17/288498

- Cambridge, GB
Mudit Bhargava - Austin TX, US
Brian Tracy Cline - Austin TX, US
Saurabh Pijuskumar Sinha - San Antonio TX, US
Gregory Munson Yeric - Austin TX, US

G02B 6/12
G02B 6/26
G02B 6/42

Disclosed are devices and techniques for facilitating transmission of light signals between optical waveguides formed on integrated circuit (IC) devices. In an implementation, one or more first waveguides may be formed in a structure such that at least a portion of the one or more first waveguides are exposed for optical connectivity. The structure may comprise first features to enable the structure to be interlocked with an IC device comprising second features complementary with the first features, so as to align at least a portion of the one or more first waveguides exposed to optically couple with one or more second waveguides formed in the first integrated circuit device.

2021008, Mar 18, 2021

Sep 12, 2019

16/569482

- Cambridge, GB
Brian Tracy Cline - Austin TX, US
Saurabh Pijuskumar Sinha - San Antonio TX, US
Stephen Lewis Moore - Austin TX, US
Mudit Bhargava - Austin TX, US

G06F 17/50

Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

2021002, Jan 28, 2021

Jul 25, 2019

16/522461

- Cambridge, GB
Saurabh Pijuskumar Sinha - San Antonio TX, US
Sheng-En Hung - Austin TX, US
Chien-Ju Chao - Austin TX, US

H03L 7/08
G06F 1/06
G06F 1/10
G06F 1/12

Disclosed are methods, systems and devices for distribution of a timing signal among operational nodes of a circuit device comprising one or more circuit dies. In one implementation, a timing signal distribution network may transmit a timing signal to one or more operational circuit nodes formed on a circuit die and a clock circuit may generate a first clock signal for transmission as the timing signal to the one or more operational circuit nodes. A switch circuit may apply a second clock signal for transmission as the timing signal in lieu of the first clock signal if the circuit die is integrated at least one of the one or more other circuit dies. In another implementation, timing signals received at timing signal terminals of at least two of two or more of operational circuit nodes may be synchronized independently of the timing signal distribution network.

2020027, Sep 3, 2020

May 18, 2020

16/877400

- Cambridge, GB
Saurabh Pijuskumar Sinha - San Antonio TX, US
Brian Tracy Cline - Austin TX, US
Stephen Lewis Moore - Austin TX, US

G06F 30/394
G06F 30/392

Implementations described herein are directed to a device with a processor and memory having stored thereon instructions that, when executed by the processor, cause the processor to acquire an integrated circuit layout of physical cells from a database and define wirelength relationships between input/output connections and a cell count for the physical cells in multiple domains. The instructions may cause the processor to define wirelength parameters of the integrated circuit layout in each domain of the multiple domains and generate a data file for the integrated circuit layout of the physical cells based on the wirelength relationships and the wirelength parameters to guide power and performance of the integrated circuit layout of the physical cells. The instructions may cause the processor to fabricate, or contribute to the fabrication of, an integrated circuit based on the data file for the integrated circuit layout of the physical cells.

2020021, Jul 9, 2020

Mar 16, 2020

16/820471

- Cambridge, GB
Brian Tracy Cline - Austin TX, US
Stephen Lewis Moore - Austin TX, US
Saurabh Pijuskumar Sinha - San Antonio TX, US

G06F 30/392
H01L 27/02
H01L 23/522

Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

2019038, Dec 19, 2019

Jun 15, 2018

16/010253

- Cambridge, GB
Shidhartha Das - Upper Cambourne, GB
Mudit Bhargava - Austin TX, US
Saurabh Pijuskumar Sinha - San Antonio TX, US
James Edwards Myers - Bottisham, GB

G11C 13/00

Disclosed are methods, systems and devices for operation of memory device. In one aspect, a signal may have an amplitude within a continuous amplitude range, and a non-volatile memory element may be placed in an impedance state representing the amplitude. The amplitude of the signal may be recovered based, at least in part, on the impedance state of the correlated electron element.