Sayed S Hasan, 4912697 NW Bayonne Ln, Portland, OR 97229

2020025, Aug 13, 2020

Feb 11, 2019

16/272816

- Santa Clara CA, US
Patrick MORROW - Portland OR, US
Sayed HASAN - Portland OR, US

H01L 27/11556
H01L 27/11519
H03K 19/23

A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

2020000, Jan 2, 2020

Jun 29, 2018

16/024064

- Santa Clara CA, US
RISHABH MEHANDRU - Portland OR, US
ANH PHAN - Beaverton OR, US
GILBERT DEWEY - Beaverton OR, US
WILLY RACHMADY - Beaverton OR, US
STEPHEN M. CEA - Hillsboro OR, US
SAYED HASAN - Portland OR, US
KERRYANN M. FOLEY - Hillsboro OR, US
PATRICK MORROW - Portland OR, US
COLIN D. LANDON - Portland OR, US
EHREN MANNEBACH - Beaverton OR, US

INTEL CORPORATION - Santa Clara CA

H01L 27/092
H01L 27/12
H01L 29/78
H01L 29/775
H01L 29/423

Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.