Scott M Becker, 49Park Ridge, IL

6597613, Jul 22, 2003

Mar 27, 2002

10/113759

Scott T. Becker - Darien IL
Betina Hold - Los Altos CA
Sudhir S. Moharir - Santa Clara CA

Artisan Components, Inc. - Sunnyvale CA

G11C 706

365207, 327 53, 327 66

A load independent single ended sense amplifier is provided. The sense amplifier includes a first current mirror having a first load transistor and a first reflected current transistor, and a second current mirror having a second load transistor and a second reflected current transistor. The first load transistor is capable of communicating a load current to the second load transistor. In addition, a reflected current flowing through the first reflected current transistor and the second reflected current transistor generates an amplified load current.

6618311, Sep 9, 2003

Feb 12, 2002

10/074559

Scott T. Becker - Darien IL

Artisan Components, Inc. - Sunnyvale CA

G11C 1718

3652257, 365200, 36523008, 36518911, 365 96, 365 94, 365102, 327525, 327526, 716 2

An invention is provided for a fuse state sensing circuit that senses the state of a fuse, which is coupled between a ground rail and a fuse state sensing node. The fuse state sensing node indicates a state of the fuse when rail voltage is provided to the fuse state sensing circuit. In addition, a capacitive element is included that is coupled to the fuse state sensing node. The capacitive element is capable of providing a first amount of current to the fuse state sensing node when an initial voltage is supplied to the rail voltage. The capacitive element is further configured to stop supplying the first amount of current upon reaching a threshold voltage of the capacitive element. The fuse state sensing circuit further includes a keeper latch circuit that is coupled to the fuse state sensing node in parallel with the capacitive element. The keeper latch circuit is capable of latching the state of the fuse state sensing node. In addition, the keeper latch circuit stops supplying current to the fuse state sensing node when a predetermined rail voltage is reached if the fuse is intact.

6788615, Sep 7, 2004

Feb 10, 2003

10/364720

Scott T. Becker - Darien IL

Artisan Components, Inc. - Sunnyvale CA

G11C 800

365233, 36523003, 365210

An invention for self-timing in a memory device is provided. The self-timing system includes a dummy global wordline signal, which is configured to follow a global timing pulse for a memory device. In addition, a row of at least one non-timing memory banks is included. Each non-timing memory bank includes a model row in electrical communication with the dummy global wordline signal. Each model row is comprised of a plurality of load cells. The self-timing system further includes a timing memory bank having a global timing column. The global timing column is comprised of a plurality of load cells that are coupled via at least one bitline. In operation, the global timing column responds to the dummy global wordline signal to provide a self-timing reset signal for the memory device. In this manner, the self-timing reset signal is provided to each active memory bank in the row of memory banks.

6833624, Dec 21, 2004

Feb 10, 2003

10/364198

Scott T. Becker - Darien IL

Artisan Components, Inc. - Sunnyvale CA

H01L 2348

257758, 257756

The invention provides overlapping row decode in a multiport memory. Overlapping row decode includes predecode wires positioned on a first metallization layer and configured to address wordline drivers of a first port. A second plurality of predecode wires is located on a third metallization layer and configured to address wordline drivers of a second port. The overlapping row decode includes a plurality of wordline connections that are formed on a second metallization layer between the first metallization layer and the third metallization layer. The wordline connections include a first and second portion. The first portion communicates with the first plurality of predecode wires and the wordline drivers of the first port. The second portion communicates with the second plurality of predecode wires and the wordline drivers of the second port.

6865119, Mar 8, 2005

Feb 10, 2003

10/364719

Scott T. Becker - Darien IL, US

Artisan Components, Inc. - Sunnyvale CA

G11C007/00

36518911, 365154, 36518909, 36523005

An invention is provided for reducing subthreshold current in memory core cells. A memory array having a plurality of memory core cells is provided. Each memory core cell in the memory array is selectable using a word line. A selected word line addressing a particular memory core cell is charged to a positive voltage. In addition, unselected wordlines of the memory array are charged to a negative voltage. In this manner, subthreshold current associated with unselected memory core cells is reduced.

6934213, Aug 23, 2005

Jun 11, 2003

10/460626

Scott T. Becker - Darien IL, US

Artisan Components, Inc. - Sunnyvale CA

G11C007/00

365227, 365145, 365156

A method and circuit for reducing power consumption during write operations in a RAM are disclosed. In A RAM comprised of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge sharing line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.

7005910, Feb 28, 2006

Jan 16, 2004

10/759339

Scott T. Becker - Darien IL, US
Brian Reed - Cupertino CA, US
Puneet Sawhney - San Jose CA, US

ARM Physical IP, Inc. - Sunnyvale CA

H03K 17/04

327374, 327375, 327376, 327377

An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

7343581, Mar 11, 2008

Jun 27, 2005

11/169188

Scott T. Becker - Darien IL, US

Tela Innovations, Inc. - Campbell CA

G06F 17/50

716 17, 716 18

A high-level logic description is developed based on a non-primitive-based standard cell library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic cells to create a primitive constructed version of each referenced standard cell. The set of primitive logic cells is defined for integration within a base array. The primitive constructed version of each referenced standard cell is included within a primitive-based cell library. The primitive-based cell library is used to place and route the netlist for the logic design for integration within the base array. The logic design is then integrated within the base array.