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Scott D Luning, 611704 Newton St, Austin, TX 78704

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1704 Newton St, Austin, TX 78704    512-4435306   

11108 Seay St, Austin, TX 78754    512-2780362   

Sacul, TX   

South Fork, CO   

Huntsville, TX   

Ballston Spa, NY   

Poughkeepsie, NY   

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Hopewell Junction, NY   

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Menlo Park, CA   

Mentions for Scott D Luning

Publications & IP owners

Us Patents

Method To Form Narrow Structure Using Double-Damascene Process

US Patent:
6355528, Mar 12, 2002
Filed:
Oct 26, 1999
Appl. No.:
09/426911
Inventors:
Emi Ishida - Sunnyvale CA
Scott Luning - Austin TX
Tim Thurgate - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438269, 438289, 438301, 438947
Abstract:
A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

Angled Halo Implant Tailoring Using Implant Mask

US Patent:
6372587, Apr 16, 2002
Filed:
May 10, 2000
Appl. No.:
09/568069
Inventors:
Jon D. Cheek - Round Rock TX
Scott D. Luning - Austin TX
Derick J. Wristers - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
H01L 21336
US Classification:
438302, 438303
Abstract:
A method is provided for forming a halo implant in a substrate adjacent one side of a structure, the method including forming the structure above a surface of the substrate, the structure having first and second edges and forming a mask defining a region adjacent the structure, the mask having a thickness above the surface and having an edge disposed a distance from the first edge of the structure. The method also includes implanting the halo implant at an angle with respect to a direction perpendicular to the surface, wherein the tangent of the angle is at least the ratio of the distance to the thickness.

Method For Forming Vertical Profile Of Polysilicon Gate Electrodes

US Patent:
6391751, May 21, 2002
Filed:
Jul 27, 2000
Appl. No.:
09/626668
Inventors:
David Donggang Wu - Austin TX
William R. Roche - Beaverton OR
Scott D. Luning - Austin TX
Karen L. E. Turnqest - Pflugerville TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
H01L 23205
US Classification:
438585, 438299, 438532
Abstract:
The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon, forming a masking layer above the layer of polysilicon, and patterning the masking layer to expose portions of the layer of polysilicon. The method further comprises implanting a dopant material into the exposed portions of the layer of polysilicon to convert the exposed portions of the layer of polysilicon to substantially amorphous silicon, and performing an etching process to remove the substantially amorphous silicon to define a gate electrode.

Control Trimming Of Hard Mask For Sub-100 Nanometer Transistor Gate

US Patent:
6482726, Nov 19, 2002
Filed:
Oct 17, 2000
Appl. No.:
09/690152
Inventors:
Massud Aminpur - Dresden, DE
David Wu - Austin TX
Scott Luning - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
H01L 213205
US Classification:
438585, 438592, 438197
Abstract:
A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. The method also includes forming a trimmed photoresist mask above the second hard mask layer, and forming a patterned hard mask in the second hard mask layer using the trimmed photoresist mask to remove portions of the second hard mask layer, the patterned hard mask having a first dimension. The method further includes forming a selectively etched hard mask in the first hard mask layer by removing portions of the first hard mask layer adjacent the patterned hard mask, the selectively etched hard mask having a second dimension less than the first dimension, and forming a gate structure using the selectively etched hard mask to remove portions of the gate conductor layer above the gate dielectric layer.

Removable Spacer Technique

US Patent:
6506642, Jan 14, 2003
Filed:
Dec 19, 2001
Appl. No.:
10/020931
Inventors:
Scott D. Luning - Austin TX
Jon D. Cheek - Round Rock TX
Daniel Kadosh - Austin TX
James F. Buller - Austin TX
David E. Brown - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 218238
US Classification:
438231, 438275, 438305, 438592, 438286
Abstract:
Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e. g. , different drive current and voltage leakage requirements.

Selective Epitaxy To Reduce Gate/Gate Dielectric Interface Roughness

US Patent:
6548335, Apr 15, 2003
Filed:
Aug 30, 2000
Appl. No.:
09/651891
Inventors:
Carl Robert Huster - San Jose CA
Concetta Riccobene - Mountain View CA
Scott Luning - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438197, 438478, 438585, 438770
Abstract:
Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Method Of Reducing Photoresist Shadowing During Angled Implants

US Patent:
6569606, May 27, 2003
Filed:
Jul 27, 2000
Appl. No.:
09/626666
Inventors:
David Donggang Wu - Austin TX
William R. Roche - Beaverton OR
Massud Aminpur - Dresden, DE
Scott D. Luning - Austin TX
Karen L. E. Turnqest - Pflugerville TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G03C 500
US Classification:
430322, 430311, 430396, 430397, 359709, 438302
Abstract:
The present invention is directed to a method of forming halo implants in a semiconductor device. In one illustrative embodiment, the method comprises forming a structure above a semiconducting substrate, forming a layer of photoresist above the structure and the substrate, and positioning the substrate in an exposure tool that has a light source and a focal plane. The method further comprises positioning the surface of the layer of photoresist in an exposure plane that is different from the focal plane of the exposure tool, exposing the photoresist to the light source of the exposure tool while the surface of the photoresist is in the exposure plane, and developing the layer of photoresist to define an opening in the layer of photoresist around the structure on the substrate.

Tilted Counter-Doped Implant To Sharpen Halo Profile

US Patent:
6589847, Jul 8, 2003
Filed:
Aug 3, 2000
Appl. No.:
09/631557
Inventors:
Daniel Kadosh - Austin TX
Scott D. Luning - Austin TX
Derick J. Wristers - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
H01L 21336
US Classification:
438302, 438305, 438525, 438301
Abstract:
The present invention is directed to a method of forming halo implant regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, the substrate being doped with a first type of dopant material, and forming halo implant regions in the substrate adjacent the gate electrode by performing at least the following steps: performing a first angled implant process using a dopant material that is of a type opposite to the first type of dopant material and performing a second angled implant using a dopant material that is of the same type as the first type of dopant material. The method concludes with performing at least one additional implantation process to further form source/drain regions for the device.

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