Sean T Ma, 56255 SW Harrison St UNIT 4H, Portland, OR 97201

2022033, Oct 20, 2022

Jun 23, 2022

17/848191

- Santa Clara CA, US
Sean Ma - Portland OR, US
Justin R. Weber - Hillsboro OR, US
Rishabh Mehandru - Portland OR, US
Stephen M. Cea - Hillsboro OR, US
Patrick Morrow - Portland OR, US
Patrick H. Keys - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 21/822
H01L 21/306
H01L 21/311
H01L 21/8238
H01L 21/8258
H01L 27/092
H01L 29/417
H01L 29/66

Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

2022032, Oct 13, 2022

May 27, 2022

17/826550

- Santa Clara CA, US
Sean T. Ma - Portland OR, US
Van H. Le - Beaverton OR, US
Jack T. Kavalieros - Portland OR, US
Gilbert Dewey - Beaverton OR, US

Intel Corporation - Santa Clara CA

H01L 29/786
H01L 29/423
H01L 29/06
H01L 29/66
H01L 29/49

Described is a thin film transistor which comprises: a dielectric comprising a dielectric material; a first structure adjacent to the dielectric, the first structure comprising a first material; a second structure adjacent to the first structure, the second structure comprising a second material wherein the second material is doped; a second dielectric adjacent to the second structure; a gate comprising a metal adjacent to the second dielectric; a spacer partially adjacent to the gate and the second dielectric; and a contact adjacent to the spacer.

2022023, Jul 28, 2022

Apr 19, 2022

17/724331

- Santa Clara CA, US
Cory WEBER - Portland OR, US
Van H. LE - Portland OR, US
Sean MA - Portland OR, US

H01L 29/47
H01L 27/108
H01L 27/24
H01L 29/423
H01L 29/66
H01L 29/786

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

2022023, Jul 21, 2022

Apr 6, 2022

17/714182

- Santa Clara CA, US
Sean T. Ma - Portland OR, US
Andy Chih-Hung Wei - Yamhill OR, US

Intel Corporation - Santa Clara CA

H01L 29/06
H01L 27/088
H01L 29/423
H01L 29/786

Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

2023011, Apr 13, 2023

Sep 24, 2021

17/485158

- Santa Clara CA, US
Biswajeet Guha - Hillsboro OR, US
Leonard Guler - Hillsboro OR, US
Tahir Ghani - Portland OR, US
Sean Ma - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 29/423
H01L 29/06
H01L 29/786
H01L 29/66

Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

2023007, Mar 9, 2023

Sep 19, 2022

17/947363

- Santa Clara CA, US
Andy Chih-Hung Wei - Yamhill OR, US
Sean T. Ma - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 27/088
H01L 21/8234

Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first dielectric material continuously around the first gate metal; and a second dielectric material continuously around the second gate metal, wherein the first dielectric material and the second dielectric material are present between the first gate metal and the second gate metal.

2023007, Mar 9, 2023

Nov 14, 2022

17/986715

- Santa Clara CA, US
Anand MURTHY - Portland OR, US
Biswajeet GUHA - Hillsboro OR, US
Dax M. CRUM - Beaverton OR, US
Sean MA - Portland OR, US
Tahir GHANI - Portland OR, US
Susmita GHOSE - Hillsboro OR, US
Stephen CEA - Hillsboro OR, US
Rishabh MEHANDRU - Portland OR, US

H01L 29/06
H01L 21/02
H01L 21/285
H01L 21/306
H01L 29/08
H01L 29/10
H01L 29/165
H01L 29/417
H01L 29/423
H01L 29/45
H01L 29/66
H01L 29/78

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

2023000, Jan 5, 2023

Aug 30, 2022

17/899429

- Santa Clara CA, US
Willy RACHMADY - Beaverton OR, US
Jack T. KAVALIEROS - Portland OR, US
Cheng-Ying HUANG - Portland OR, US
Matthew V. METZ - Portland OR, US
Sean T. MA - Portland OR, US
Harold KENNEL - Portland OR, US
Tahir GHANI - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 29/78
H01L 29/20
H01L 29/423
H01L 29/66
H01L 29/51
H01L 21/28

Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.