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Shailendra S Desai, 53San Jose, CA

Related to:
Priya Sheth 49 Neha Sheth 53

Shailendra Desai Phones & Addresses

San Jose, CA   

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Career records & work history

Medicine Doctors

Shailendra A. Desai

Specialties:
Diagnostic Radiology
Work:
Center For Diagnostic Imaging
1450 E Chestnut Ave STE 4C, Vineland, NJ 08361
856-7941700 (phone) 856-7941788 (fax)
Site
Center For Diagnostic Imaging
1119 Hwy 77 STE C, Bridgeton, NJ 08302
856-4531555 (phone) 856-7942671 (fax)
Site
Education:
Medical School
J L Nehru Med Coll, R Gandhi Univ Hlth Sci, Belgaum, Karnataka, India
Graduated: 1975
Languages:
English, Spanish
Description:
Dr. Desai graduated from the J L Nehru Med Coll, R Gandhi Univ Hlth Sci, Belgaum, Karnataka, India in 1975. He works in Bridgeton, NJ and 1 other location and specializes in Diagnostic Radiology.
Shailendra Desai Photo 1

Shailendra Ashraylal Desai

Specialties:
Radiology
Diagnostic Radiology
Education:
(1976)

License Records

Shailendra Ashraylal Desai

Licenses:
License #: MT000974T - Expired
Category: Medicine
Type: Graduate Medical Trainee

Shailendra Desai resumes & CV records

Resumes

Shailendra Desai Photo 20

Chief Executive Officer And Founder

Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Provino Technologies
Chief Executive Officer and Founder Apple 2008 - Jan 2013
Senior Engineer Manager Pa Semi Jul 2004 - Apr 2008
Senior Engineer Manager Sibyte 1999 - 2004
Principal Engineer Broadcom 1999 - 2003
Principal Engineer Lsi Corporation 1992 - 1997
Design Engineer
Education:
Santa Clara University 1992 - 1994
Master of Science, Masters, Computer Engineering Sardar Vallabhbhai National Institute of Technology, Surat 1987 - 1991
Bachelor of Engineering, Bachelors, Electrical Engineering
Skills:
Asic, Soc, Verilog, Eda, Debugging, Vlsi, Semiconductors, Processors, Ic, Embedded Systems, Hardware Architecture, Computer Architecture, Integrated Circuits, Microarchitecture, Microprocessors, Static Timing Analysis, Application Specific Integrated Circuits, Field Programmable Gate Arrays, System on A Chip, Fpga, Physical Design, Timing Closure, Low Power Design
Shailendra Desai Photo 21

Shailendra Desai

Publications & IP owners

Us Patents

Default Bus Grant To A Bus Agent

US Patent:
7076586, Jul 11, 2006
Filed:
Oct 6, 2000
Appl. No.:
09/680757
Inventors:
Joseph B. Rowlands - Santa Clara CA, US
Shailendra S. Desai - San Jose CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 13/36
US Classification:
710113, 710309
Abstract:
A system may include two or more agents, one of which may be identified as a default agent. If none of the agents arbitrate for the bus, the default agent may be given a default grant of the bus. If the default agent has information to transfer on the bus, the default agent may take the default grant and my transfer the information without first arbitrating for the bus and winning the arbitration. In one embodiment, the default agent may arbitrate for the bus when it has information to transfer and no default grant is received. The default agent may be an equal participant in arbitration. A fair arbitration scheme may thus be implemented in arbitrations in which there is contention for the bus.

System On A Chip For Packet Processing

US Patent:
7287649, Oct 30, 2007
Filed:
May 18, 2001
Appl. No.:
09/861188
Inventors:
Mark D. Hayter - Menlo Park CA, US
Shailendra S. Desai - San Jose CA, US
Daniel W. Dobberpuhl - Menlo Park CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 13/00
US Classification:
209218
Abstract:
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

System On A Chip For Caching Of Data Packets Based On A Cache Miss/Hit And A State Of A Control Signal

US Patent:
7320022, Jan 15, 2008
Filed:
Jul 25, 2002
Appl. No.:
10/202753
Inventors:
Mark D. Hayter - Menlo Park CA, US
Shailendra S. Desai - San Jose CA, US
Daniel W. Dobberpuhl - Menlo Park CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 13/00
US Classification:
709215
Abstract:
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.

Network Direct Memory Access

US Patent:
7836220, Nov 16, 2010
Filed:
Aug 17, 2006
Appl. No.:
11/505736
Inventors:
Shailendra S. Desai - San Jose CA, US
Mark D. Hayter - Menlo Park CA, US
Dominic Go - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 13/28
G06F 15/16
G06F 15/167
US Classification:
710 22, 710 26, 709216, 709218
Abstract:
In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Network Direct Memory Access

US Patent:
8495257, Jul 23, 2013
Filed:
Oct 20, 2010
Appl. No.:
12/908741
Inventors:
Shailendra S. Desai - San Jose CA, US
Mark D. Hayter - Menlo Park CA, US
Dominic Go - San Jose CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G06F 13/28
G06F 15/167
US Classification:
710 22, 710 26, 709216
Abstract:
In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

Fast Arbitration Scheme For A Bus

US Patent:
2005017, Aug 4, 2005
Filed:
Mar 1, 2005
Appl. No.:
11/069359
Inventors:
Joseph Rowlands - Santa Clara CA, US
David Anderson - Santa Clara CA, US
Shailendra Desai - San Jose CA, US
International Classification:
G06F013/00
US Classification:
710240000
Abstract:
A distributed arbitration scheme includes arbiters with each agent. The arbiters receive request signals indicating which agents are arbitrating for the bus. Additionally, the agent currently using the bus broadcasts an agent identifier assigned to that agent. The arbiters receive the agent identifier and use the agent identifier as an indication of the winner of the preceding arbitration. Accordingly, the arbiters determine if the corresponding agent wins the arbitration, but may not attempt to calculate which other agent wins the arbitration. In one embodiment, the arbiter maintains a priority state indicative of which of the other agents are higher priority than the corresponding agent and which of the other agents are lower priority. In one implementation, the bus may be a split transaction bus and thus each requesting agent may include an address arbiter and each responding agent may include a data arbiter.

Channelized Flow Control

US Patent:
2007004, Mar 1, 2007
Filed:
Aug 25, 2005
Appl. No.:
11/212075
Inventors:
Shailendra Desai - San Jose CA, US
Mark Hayter - Menlo Park CA, US
Assignee:
P.A. Semi, Inc. - Santa Clara CA
International Classification:
H04J 1/16
US Classification:
370235000
Abstract:
In one embodiment, a controller is configured to receive a flow control packet from a link partner on a communication medium. The flow control packet includes a channel indication that indicates one or more channels. The controller is configured to inhibit transmission of packets from at least one channel specified by the channel indication and to permit transmission of packets from channels not specified in the channel indication. The controller may also be configured to transmit the flow control packet in response to detecting a need to flow control one or more channels from the link partner.

Explicit Flow Control In Gigabit/10 Gigabit Ethernet System

US Patent:
2007004, Mar 1, 2007
Filed:
Aug 25, 2005
Appl. No.:
11/211259
Inventors:
Shailendra Desai - San Jose CA, US
Mark Hayter - Menlo Park CA, US
Assignee:
P.A. Semi, Inc. - Santa Clara CA
International Classification:
H04L 12/66
H04J 3/16
US Classification:
370463000, 370469000
Abstract:
In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.

Possible Relatives

Daxa R Desai  Daksha D Desai  Darshan P Desai  Devang R Desai  Devendra V Desai  Dharmesh Desai  Dhaval Desai  Shailendra J Patel  Shailendra J Ram  Shailendra A Guptaa 

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