Sherman M Dance, 6512105 Oak Ave SW, Pleasant Grove, MN 55976

7716264, May 11, 2010

Aug 16, 2005

11/205987

Sherman M. Dance - Rochester MN, US
Jeffrey R. Summers - Raleigh NC, US
Shivakumar Swaminathan - Morrisville NC, US

International Business Machines Corporation - Armonk NY

G06F 15/00

708209, 708505

An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.

7958180, Jun 7, 2011

Jul 5, 2007

11/773558

Douglas H. Bradley - Austin TX, US
Owen Chiang - Austin TX, US
Sherman M. Dance - Rochester MN, US

International Business Machines Corporation - Armonk NY

G06F 7/52

708620

A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit position.

2007001, Jan 11, 2007

Jul 7, 2005

11/178073

Sherman Dance - Rochester MN, US
Jeffrey Summers - Raleigh NC, US
Shivakumar Swaminathan - Morrisville NC, US

G06F 7/00

708603000

A system and method for processing single-precision floating-point numbers. The system includes a processor that has a double-precision (DP) register, wherein the DP register receives a plurality of single-precision (SP) operands, and a recoder coupled to the DP register, wherein the recoder recodes a first SP operand of the plurality of SP operands. The processor also includes a plurality of partial product (PP) units coupled to the DP register, wherein each PP unit of the plurality of PP units processes a second SP operand of the plurality of SP operands.

2007011, May 17, 2007

Nov 17, 2005

11/282032

Sherman Dance - Rochester MN, US
Andrew Freemyer - Rochester MN, US
Matthew Tubbs - Rochester MN, US

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

G06F 7/552

708500000

In a first aspect, a first method of reciprocal estimate computation using floating point pipeline logic is provided. The first method includes the steps of (1) receiving an input value having an exponent and a mantissa when represented as a floating point number on which a reciprocal estimate computation is to be performed; (2) determining whether the exponent is one of a plurality of predetermined numbers; and (3) if the exponent is one of the plurality of predetermined numbers, adjusting at least one of a plurality of modified mantissa bits (e.g., mantissa bits internal to leading zero anticipator (LZA) logic) and the exponent so as to prevent an underflow result of the reciprocal estimate computation. Numerous other aspects are provided.