Inventors:
Shivani Gupta - Milpitas CA
Christina Phan - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G05F 110
Abstract:
An integrated circuit having at least one segmented array of switches, wherein the root node of each segmented array of switches is a node whose potential varies with time during operation. Each segmented switch array includes switches connected between nodes having a tree structure. The nodes include the root node and additional nodes of at least two different degrees relative to the root node. By providing a segmented array (rather than a non-segmented array) of switches at a node, the total load capacitance (including parasitic capacitance) at the node is reduced in accordance with the invention. In preferred embodiments, the invention is an analog integrated circuit having a first node at which the potential varies rapidly, and a segmented array of switches whose root node is the first node. Another aspect of the invention is a method for designing an integrated circuit to have reduced load capacitance (e. g. , load capacitance due to parasitic capacitance) at at least one sensitive node, including the steps of identifying a sensitive node of a preliminary design for the circuit, wherein an array of switches is coupled to the sensitive node; and determining a refined design for the circuit in which the array is replaced by a segmented switch array comprising switches connected between nodes having a tree structure, wherein the nodes include a root node, and the root node is the sensitive node.