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Simon Chan, 29San Francisco, CA

Related to:
Heidi Chan 55 Mark Philip Chan 53 Markphilip P Chan Jenalene C Chan 53

Simon Chan Phones & Addresses

San Francisco, CA   

Houston, TX   

3828 Pebble Beach Ct, The Colony, TX 75056    469-3212086   

College Station, TX   

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Mentions for Simon Chan

Career records & work history

Lawyers & Attorneys

Simon Chan Photo 1

Simon Chan - Lawyer

Office:
Allen & Overy LLP
ISLN:
920293407
Simon Chan Photo 2

Simon Chan - Lawyer

Specialties:
Government, Real Estate, Trusts/Estates/Wills, Real Estate, Trusts/Estates/Wills
ISLN:
923297938
Admitted:
2013

Medicine Doctors

Simon C. Chan

Specialties:
Internal Medicine
Work:
Anne Chen Inc & Dr Simon Chan
2560 N Texas St STE C, Fairfield, CA 94533
707-4234355 (phone) 707-4234353 (fax)
Education:
Medical School
New York University School of Medicine
Graduated: 1995
Procedures:
Destruction of Benign/Premalignant Skin Lesions, Electrocardiogram (EKG or ECG), Vaccine Administration
Conditions:
Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Hypertension (HTN), Ischemic Heart Disease, Acute Bronchitis, Acute Pharyngitis, Acute Sinusitis, Acute Upper Respiratory Tract Infections, Anemia, Angina Pectoris, Anxiety Dissociative and Somatoform Disorders, Anxiety Phobic Disorders, Aortic Aneurism, Aortic Valvular Disease, Atrial Fibrillation and Atrial Flutter, Bacterial Pneumonia, Benign Prostatic Hypertrophy, Bronchial Asthma, Cardiac Arrhythmia, Cataract, Chronic Renal Disease, Constipation, Contact Dermatitis, Depressive Disorders, Dermatitis, Erectile Dysfunction (ED), Esophagitis, Fractures, Dislocations, Derangement, and Sprains, Gastroesophageal Reflux Disease (GERD), Gout, Hearing Loss, Hemorrhoids, Hyperthyroidism, Hypothyroidism, Infectious Liver Disease, Inguinal Hernia, Intestinal Obstruction, Irritable Bowel Syndrome (IBS), Lateral Epicondylitis, Menopausal and Postmenopausal Disorders, Migraine Headache, Obstructive Sleep Apnea, Osteoarthritis, Osteoporosis, Otitis Media, Overweight and Obesity, Parkinson's Disease, Peripheral Nerve Disorders, Plantar Fascitis, Plantar Warts, Psoriasis, Sciatica, Skin and Subcutaneous Infections, Substance Abuse and/or Dependency, Urinary Incontinence, Urinary Tract Infection (UT), Varicose Veins, Venous Embolism and Thrombosis
Languages:
English, Spanish
Description:
Dr. Chan graduated from the New York University School of Medicine in 1995. He works in Fairfield, CA and specializes in Internal Medicine. Dr. Chan is affiliated with NorthBay Medical Center and Sutter Solano Medical Center.

Simon S. Chan

Specialties:
Gastroenterology, Internal Medicine
Work:
Princeton Physicians Associates
500 N Garfield Ave STE 308, Monterey Park, CA 91754
626-2888292 (phone) 626-2888789 (fax)
Simon S Chan MD
436 N Bedford Dr STE 218, Beverly Hills, CA 90210
310-2880182 (phone) 310-2880183 (fax)
Education:
Medical School
Mount Sinai School of Medicine
Graduated: 1984
Languages:
Chinese, English
Description:
Dr. Chan graduated from the Mount Sinai School of Medicine in 1984. He works in Beverly Hills, CA and 1 other location and specializes in Gastroenterology and Internal Medicine. Dr. Chan is affiliated with Alhambra Hospital Medical Center, Cedars-Sinai Medical Center and Ronald Reagan UCLA Medical Center.
Simon Chan Photo 3

Simon Chi Yan Chan

Specialties:
Internal Medicine
Gastroenterology
Education:
New York University (1995)

License Records

Simon Chan

Licenses:
License #: FMC00134 - Expired
Category: Food Safety
Issued Date: Aug 9, 1993
Expiration Date: Jan 31, 1999
Type: Certified Food Safety Mgr

Publications & IP owners

Us Patents

Low Stress Sidewall Spacer In Integrated Circuit Technology

US Patent:
7005357, Feb 28, 2006
Filed:
Jan 12, 2004
Appl. No.:
10/756023
Inventors:
Minh Van Ngo - Fremont CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Paul R. Besser - Sunnyvale CA, US
Paul L. King - Mountain View CA, US
Errol Todd Ryan - Wappingers Falls NY, US
Robert J. Chiu - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/336
H01L 21/441
US Classification:
438303, 438595, 438682, 438683
Abstract:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

Selectable Open Circuit And Anti-Fuse Element, And Fabrication Method Therefor

US Patent:
7015076, Mar 21, 2006
Filed:
Mar 1, 2004
Appl. No.:
10/791098
Inventors:
Darin A. Chan - San Francisco CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Paul L. King - Mountain View CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21/82
US Classification:
438131, 438467, 438600, 438630, 438770, 257530, 257209
Abstract:
A method is provided of forming an integrated circuit with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is deposited above the semiconductor substrate. Contacts and connection points are then formed in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Trenches To Reduce Lateral Silicide Growth In Integrated Circuit Technology

US Patent:
7023059, Apr 4, 2006
Filed:
Mar 1, 2004
Appl. No.:
10/791094
Inventors:
Darin A. Chan - San Francisco CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Jeffrey P. Patton - Santa Clara CA, US
Jacques J. Bertrand - Capitola CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29/94
US Classification:
257382, 257213, 257288, 257368, 257386, 257387, 257388, 438584, 438597, 438682, 438683
Abstract:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

Method For Achieving Increased Control Over Interconnect Line Thickness Across A Wafer And Between Wafers

US Patent:
7122465, Oct 17, 2006
Filed:
Dec 2, 2004
Appl. No.:
11/003208
Inventors:
Cinti Xiaohua Chen - Fremont CA, US
Simon S. Chan - Saratoga CA, US
Inkuk Kang - San Jose CA, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/4763
US Classification:
438633, 438687, 438692, 257E21304
Abstract:
According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Selectable Open Circuit And Anti-Fuse Element

US Patent:
7250667, Jul 31, 2007
Filed:
Jan 5, 2006
Appl. No.:
11/306663
Inventors:
Darin A. Chan - San Francisco CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Paul L. King - Mountain View CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29/00
US Classification:
257499, 257528, 257529
Abstract:
An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a silicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Method Of Reducing Stress Corrosion Induced Voiding Of Patterned Metal Layers

US Patent:
2001000, Jul 12, 2001
Filed:
Jan 22, 2001
Appl. No.:
09/765426
Inventors:
Minh Ngo - Union City CA, US
Simon Chan - Saratoga CA, US
Anne Sanderfer - Campbell CA, US
King Ko - San Jose CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L021/4763
US Classification:
438/622000
Abstract:
Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400 C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.

Method Of Forming Planarized Shallow Trench Isolation

US Patent:
2005015, Jul 21, 2005
Filed:
Jan 20, 2004
Appl. No.:
10/759207
Inventors:
Darin Chan - San Francisco CA, US
Simon Chan - Saratoga CA, US
Angela Hui - Fremont CA, US
International Classification:
H01L021/76
H01L021/336
US Classification:
438424000, 438435000, 438296000
Abstract:
Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

Integrated Circuit System With Implant Oxide

US Patent:
2008014, Jun 19, 2008
Filed:
Dec 16, 2006
Appl. No.:
11/611860
Inventors:
Shenqing Fang - Fremont CA, US
Rinji Sugino - San Jose CA, US
Jayendra Bhakta - Sunnyvale CA, US
Takashi Orimoto - Sunnyvale CA, US
Hiroyuki Nansei - Fukushima-ken, JP
Yukio Hayakawa - Cupertino CA, US
Hidehiko Shiraiwa - San Jose CA, US
Takayuki Maruyama - Fukushima-ken, JP
Kuo-Tung Chang - Saratoga CA, US
YouSeok Suh - Cupertino CA, US
Amol Ramesh Joshi - Sunnyvale CA, US
Harpreet Sachar - Milpitas CA, US
Simon Siu-Sing Chan - Saratoga CA, US
Assignee:
Spansion LLC - Sunnyvale CA
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29/792
H01L 21/3205
US Classification:
257324, 438596, 257E21294, 257E29309
Abstract:
A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.

Isbn (Books And Publications)

Spiritual Theology: A Systematic Study Of The Christian Life

Author:
Simon Chan
ISBN #:
0830815422

Liturgical Theology: The Church As Worshiping Community

Author:
Simon Chan
ISBN #:
0830827633

Possible Relatives

Cynthia Chan  David C Chan  De C Chan  Deana M Chan  Dai C Chan  Deborah H Chan  Daniel S Chan  Simon A Johnson  Simon E Johnston  Simon H Stang 

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