Siu Y Chan, 771340 Pecan Grove Dr, Diamond Bar, CA 91765

8630120, Jan 14, 2014

Oct 20, 2011

13/277915

Min She - Fremont CA, US
Yan Li - Milpitas CA, US
Kwang-Ho Kim - Pleasanton CA, US
Siu Lung Chan - San Jose CA, US

SanDisk Technologies Inc. - Plano TX

G11C 11/34

36518518, 36518524, 365207

A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

2013010, Apr 25, 2013

Oct 20, 2011

13/277966

Min She - Fremont CA, US
Yan Li - Milpitas CA, US
Kwang-Ho Kim - Pleasanton CA, US
Siu Lung Chan - San Jose CA, US

G11C 16/10

36518518

A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

2014022, Aug 14, 2014

Apr 19, 2014

14/256961

- PLANO TX, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US
Kwang Ho Kim - Pleasanton CA, US
Man Lung Mui - Santa Clara CA, US

SANDISK TECHNOLOGIES, INC. - PLANO TX

G11C 16/28

36518511, 36518521

Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.

2014013, May 15, 2014

Jan 31, 2013

13/755894

- Plano TX, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US
Kwang Ho Kim - Pleasanton CA, US
Man Lung Mui - Santa Clara CA, US

SANDISK TECHNOLOGIES, INC. - Plano TX

G11C 16/28

36518511, 36518521

Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria. The sensing criteria may comprise a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a die or memory plane. Prior to performing a read or verify operation on a group of memory cells, a bit line read voltage used during sensing of the group of memory cells may be determined based on the plurality of bit line read voltages and a zone associated with the group of memory cells.

2014013, May 15, 2014

Jan 31, 2013

13/755905

- Plano TX, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US
Kwang Ho Kim - Pleasanton CA, US
Man Lung Mui - Santa Clara CA, US

SANDISK TECHNOLOGIES, INC. - Plano TX

G11C 16/28

36518511, 36518521

Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die. In some embodiments, for each die or memory plane on a die, a plurality of bit line read voltages associated with a plurality of zones may be determined based on sensing criteria such as a number of fail bits. Each zone of the plurality of zones may be associated with a memory array region within a memory plane. Within each zone, different bit line read voltages may be applied to different bit line groupings in order to compensate for systematic variations in bit line resistance between neighboring bit lines due to the use of multiple patterning lithography techniques such as spacer-based double patterning.