Position:
ASIC Design & Verification at Syndiant, Inc
Work:
Syndiant, Inc
since Dec 2009
ASIC Design & Verification
Intel Corporation
Jul 2009 - Dec 2009
Intern (FPGA Engineer)
Texas Instruments
Jul 2006 - Apr 2009
Senior IC design engineer
Maxim Integrated Products
Jun 2001 - Jul 2006
IC design engineer
Education:
Texas A&M University 1999 - 2001
Masters in Electrical Engineering, Electrical EngineeringCollege Station
Bangladesh University of Engineering and Technology
Skills:
Verilog, Verilog-A, SystemVerilog, SystemVerilog OVM, VHDL, Spice, Design Compiler, RTL Compiler, DFT Compiler, SureCOV, FastSCAN, TetraMAX, Primetime, CeltIC NDC, Formality, Pearl, Conformal, ModelSIM, PowerTHEATER, Analog Artist, Spectre, Virtuoso, Debussy, PSL, SureLINT, Cadence Incisive, SoC Encounter, Mentor-ADMS, Cadencce-AMS, Xilinx ISE, Altera Quartus, Java (Sun Certified Java Programmer & Web Componet Developer), C, C++, PERL, TCL, MATLAB, FORTRAN, UNIX, LINUX, DOS, SunSOLARIS