Dong Soo Lee, 54Russellville, AR

2022018, Jun 9, 2022

Dec 8, 2020

17/115562

- Dallas TX, US
Dong Seup LEE - McKinney TX, US

H01L 29/20
H01L 29/51
H01L 29/06

A semiconductor structure includes a first transistor including a gate structure, a drain, and a source. The gate structure of the first transistor includes a nitride-based semiconductor layer. The semiconductor structure further includes a second transistor including a gate structure, a drain, and a source. The gate structure of the second transistor also includes a nitride-based semiconductor layer. The nitride-based semiconductor layer of the first transistor's gate structure is continuous with the nitride-based semiconductor layer of the second transistor's gate structure.

2022018, Jun 9, 2022

Dec 3, 2020

17/110811

- Dallas TX, US
Dong Seup Lee - McKinney TX, US
Andinet Tefera Desalegn - Dallas TX, US

H01L 29/66
H01L 29/778
H01L 21/02
H01L 29/205
H01L 29/207
H01L 29/06

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

2023006, Mar 2, 2023

Oct 20, 2022

18/048167

- Dallas TX, US
Dong Seup Lee - McKinney TX, US
Andinet Tefera Desalegn - Dallas TX, US

H01L 29/66
H01L 29/778
H01L 21/02
H01L 29/205
H01L 29/207
H01L 29/06

In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

2019031, Oct 17, 2019

Jun 28, 2019

16/456040

- Dallas TX, US
DONG SEUP LEE - MCKINNEY TX, US
JUNGWOO JOH - ALLEN TX, US
NAVEEN TIPIRNENI - PLANO TX, US
SAMEER PRAKASH PENDHARKAR - ALLEN TX, US

H01L 29/66
H01L 29/10
H01L 29/778
H01L 27/06
H01L 21/8252
H01L 23/535
H01L 27/085

One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

2018032, Nov 8, 2018

May 4, 2017

15/587021

- Dallas TX, US
DONG SEUP LEE - MCKINNEY TX, US
JUNGWOO JOH - ALLEN TX, US
NAVEEN TIPIRNENI - PLANO TX, US
SAMEER PRAKASH PENDHARKAR - ALLEN TX, US

H01L 29/778
H01L 29/20
H01L 29/205
H01L 23/535
H01L 27/06
H01L 29/66
H01L 29/88
H01L 29/49

An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.