Stephen AuLos Altos, CA

6362688, Mar 26, 2002

Apr 26, 2000

09/559246

Stephen Au - Mountain View CA

Maxim Integrated Products, Inc. - Sunnyvale CA

H03F 345

330261, 330253, 323313, 323314

A system and method of biasing a telescopic cascode operational transconductance amplifier is provided to prevent or reduce the likelihood that the inputs to the amplifier do exceed the input common mode voltage range for the amplifier. The system and method provides a bias control circuit for the differential input transistors and tail current transistor of the operational amplifier such that their respective Vds-Vdsat is maintained substantially constant. To accomplish this, the biasing system and method uses a bandgap voltage source that typically produces a highly stable voltage that is substantially temperature and process invariant. The bandgap voltage source is used to generate bias voltages applied to the gates and drains of the differential input transistors that maintains their and the tail current transistors Vds-Vdsat substantially constant. There are several advantages of the system and method for biasing a telescopic cascode OTA. First, by keeping Vds-Vdsat substantially constant for the tail current transistor, this transistor is prevented from operating in its linear region, which would otherwise cause a decrease in the bandwidth of the amplifier.

7366825, Apr 29, 2008

Apr 26, 2005

11/115004

Gregory G. Williams - Menlo Park CA, US
Harjit Singh - Redmond WA, US
Michael G. Love - San Francisco CA, US
Stephen Z. Au - San Jose CA, US

Microsoft Corporation - Redmond WA

G06F 12/00

711103, 711156, 711170, 714 3

A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

7461312, Dec 2, 2008

Jul 22, 2004

10/897058

John A. Tardif - San Jose CA, US
Stephen Z. Au - San Jose CA, US
Eiko Junus - San Jose CA, US

Microsoft Corporation - Redmond WA

G01R 31/28

714732, 714 45, 714716, 714733, 714724, 714734, 714750, 714718

A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each time period using an incrementing value, and make that tag and the signature readable by a test controller. The MISR has the flexibility to be reset to a known initial state (or otherwise load a seed value) at the beginning of each time period or to continue accumulating signatures without being reset (or using the seed value). Accumulation of signatures over an extended period of time allows a test controller to validate that no errors occurred during a long term test without having to closely monitor the intermediate results.

6008689, Dec 28, 1999

May 28, 1998

9/086977

Stephen C. Au - Mountain View CA
David Maes - Santa Clara CA
Chowdhury F. Rahim - Saratoga CA

Maxim Integrated Products, Inc. - Sunnyvale CA

H03K 301

327534

The present invention provides a switch circuit having a switch and a first body grabbing circuit. The switch includes a first transistor and a second transistor. The first transistor has a body and is coupled to the second transistor in parallel to form a common source and a common drain. The common source defines an input node and the common drain defines an output node. The first body grabbing circuit is coupled to the body of the first transistor. The first body grabbing circuit is arranged to couple the body of the first transistor to the input node when the first and second transistors receive a turn-on voltage signal such that a body effect is eliminated in the first transistor.

2015014, May 21, 2015

Nov 21, 2013

14/086860

- Redmond WA, US
Stephen Z. Au - Union City CA, US
Thomas Zou - Millbrae CA, US
Tracy Sharpe - Seattle WA, US

Microsoft Corporation - Redmond WA

G06F 13/32
G06F 13/38

710308

One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA bus. The interconnect chip may communicate with the IO device via the AMBA bus in an AMBA compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA bus, receiving a response from the IO device over the AMBA bus, and sending over the AMBA bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.