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Stephen C Bowyer, 539012 Breeland Way, Raleigh, NC 27613

Known as:
Stephen Charles Bowyer Steve C Bowyer
Related to:
Kevin Bowyer Mackenzie L Patrick 26

Stephen Bowyer Phones & Addresses

9012 Breeland Way, Raleigh, NC 27613    919-8441716   

562 Rangeley Dr, Raleigh, NC 27609    919-8441716   

5621 Rangeley Dr, Raleigh, NC 27609    919-8441716   

948 Eagle Dr, Rock Hill, SC 29732    803-3288520   

Hillsborough, NC   

Spartanburg, SC   

Work

Position: Construction and Extraction Occupations

Education

Degree: Graduate or professional degree
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Stephen Bowyer resumes & CV records

Resumes

Stephen Bowyer Photo 27

Senior Principal Engineer

Location:
1050 Enterprise Way, Sunnyvale, CA 94089
Industry:
Semiconductors
Work:
Rambus since Jul 2010
Principal Engineer siXis, Inc. Apr 2009 - Apr 2010
Senior Engineer Qimonda Jun 2006 - Dec 2008
Principal IC Design Engineer for Graphics DRAM Infineon Technologies Jul 1999 - Jun 2006
Principal IC Design Engineer for Low Power DRAM Mitsubishi Semiconductor America, Inc. Jul 1994 - Jul 1999
Senior IC Design Engineer
Education:
North Carolina State University 1999 - 2003
MS, Electrical Engineering Clemson University 1990 - 1994
BS, Electrical Engineering
Skills:
Ic, Semiconductors, Mixed Signal, Verilog, Analog, Fpga, Circuit Design, Cmos, Embedded Systems, Integrated Circuit Design, Dram, Product Development, Simulations, Soc
Stephen Bowyer Photo 28

Principal Engineer At Rambus

Location:
Raleigh-Durham, North Carolina Area
Industry:
Semiconductors

Publications & IP owners

Us Patents

Bank Address Mapping According To Bank Retention Time In Dynamic Random Access Memories

US Patent:
6920523, Jul 19, 2005
Filed:
Oct 7, 2002
Appl. No.:
10/265964
Inventors:
Stephen Bowyer - Raleigh NC, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
G06F012/00
US Classification:
711106, 711 5, 711158, 711165, 711202
Abstract:
A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

Oscillator With Temperature Control

US Patent:
7123105, Oct 17, 2006
Filed:
Dec 19, 2003
Appl. No.:
10/739398
Inventors:
Jung Pill Kim - Cary NC, US
Jens Christopher Egerer - Munich, DE
Stephen Bowyer - Raleigh NC, US
Assignee:
Infineon Technologies North American Corporation - San Jose CA
International Classification:
H03K 3/02
US Classification:
331 66, 331176, 331143, 365222
Abstract:
An oscillator circuit includes a capacitor device, a current source for supplying a current to the capacitor device, a reference voltage, and a control circuit. The reference voltage is a first input to a comparator. An output of the capacitor device and an output of the current source are a second input to the comparator. The control circuit resets the oscillator circuit when the first and second inputs to the comparator are equal.

Internal Voltage Generator With Temperature Control

US Patent:
7266031, Sep 4, 2007
Filed:
Nov 19, 2003
Appl. No.:
10/716749
Inventors:
Jung Pill Kim - Cary NC, US
Jong-Hoon Oh - Chapel Hill NC, US
Stephen Bowyer - Raleigh NC, US
George Alexander - Durham NC, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
G11C 7/04
G11C 7/00
US Classification:
365211, 36518909, 365226, 36523006
Abstract:
Methods and apparatus for varying one or more internally generated voltages of a memory device based on the temperature of the memory device are provided. The device temperature may be measured directly, for example, via an on-chip temperature sensor, or may be supplied as bits in a mode register containing temperature information.

Method And Apparatus For Reducing Standby Current In A Dynamic Random Access Memory During Self Refresh

US Patent:
7366047, Apr 29, 2008
Filed:
Nov 9, 2005
Appl. No.:
11/270178
Inventors:
Stephen Bowyer - Raleigh NC, US
Jan Zieleman - Cary NC, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
G11C 7/00
US Classification:
365222, 365203, 365205, 365207, 365208
Abstract:
A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least one of the first dynamic random access memory cell and the second dynamic random access memory cell in an idle state and to couple the sense amplifier to only the second dynamic random access memory cell to be refreshed in a refresh state.

Method And Apparatus For Using A Variable Page Length In A Memory

US Patent:
8060705, Nov 15, 2011
Filed:
Dec 14, 2007
Appl. No.:
11/957307
Inventors:
Stephen Bowyer - Raleigh NC, US
Assignee:
Qimonda AG - Munich
International Classification:
G06F 13/00
US Classification:
711154, 711E12003
Abstract:
A controller, a memory device including a memory array, and a method for accessing the memory device. The method includes, during a first access, activating a first page of the memory array corresponding to a first row address and accessing data from the first page with a first column address. The method further includes, during a second access, activating a first sub-page of the memory array corresponding to a second row address and accessing data from the first sub-page with a second column address. The activated first sub-page of the memory array is smaller than the first page of the memory array. The method further includes activating a second sub-page without receiving a separate activate command.

Error Correction Circuit And Method

US Patent:
2006019, Aug 31, 2006
Filed:
Feb 17, 2005
Appl. No.:
11/059899
Inventors:
Stephen Bowyer - Raleigh NC, US
Alan Daniel - Durham NC, US
International Classification:
G06F 11/00
H03M 13/00
US Classification:
714800000
Abstract:
The present invention includes an error correction circuit with a data memory, a write tree, a parity memory, and a read tree. The data memory is configured to hold a set of data. The write tree is configured to receive the set of data and to generate parity data. The parity memory is coupled to the write tree and is configured to receive and hold parity data. The read tree is configured to receive data from the data memory and parity data from the parity memory. The read tree is configured to generate an indication of whether an error has occurred in the data during storage within the data memory.

Memory Controller And Memory Device Command Protocol

US Patent:
2013013, May 23, 2013
Filed:
Oct 16, 2012
Appl. No.:
13/653033
Inventors:
Brent Haukness - Monte Sereno CA, US
Stephen Charles Bowyer - Raleigh NC, US
Assignee:
RAMBUS INC. - Sunnyvale CA
International Classification:
G06F 12/00
US Classification:
711154
Abstract:
Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.

Memory Controller And Memory Device Command Protocol

US Patent:
2016000, Jan 7, 2016
Filed:
Aug 21, 2015
Appl. No.:
14/833028
Inventors:
- Sunnyvale CA, US
Brent Haukness - Monte Sereno CA, US
Stephen Charles Bowyer - Raleigh NC, US
International Classification:
G11C 11/4096
G11C 11/4091
G11C 11/408
Abstract:
Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.

Possible Relatives

David R Bowyer  Debra M Bowyer  Daniel G Bowyer  Danny D Bowyer  Darla C Bowyer  Donna W Bowyer  Earl M Bowyer  Stephen H Last  Stephen V Johnson  Stephen Stamps 

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