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Stephen D Ennis, 462022 Shadetree Ln, Escondido, CA 92029

Known as:
Stephen Ennis Day
Related to:
Patrick Ennis 58 John M Perry 71

Stephen Ennis Phones & Addresses

Escondido, CA   

Alameda, CA   

Santa Cruz, CA   

San Diego, CA   

2114 President St, Palatka, FL 32177   

San Francisco, CA   

Scottsdale, AZ   

Linthicum Heights, MD   

Santa Barbara, CA   

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Stephen Ennis resumes & CV records

Resumes

Stephen Ennis Photo 43

Emergency Room Technician

Location:
Alameda, CA
Industry:
Airlines/Aviation
Work:
Suisun City Fire Department
Volunteer Firefighter and Emt, Phlebotomist
Emergency Room Technician
Education:
Bay Area Medical Academy 2018 - 2018
Skills:
Venipuncture, Emergency Management, Customer Service, Microsoft Office
Stephen Ennis Photo 44

Stephen Ennis

Stephen Ennis Photo 45

Stephen Ennis

Location:
United States
Stephen Ennis Photo 46

Sous Chef At Las Villas Del Norte

Location:
Greater San Diego Area
Industry:
Food Production
Stephen Ennis Photo 47

Stephen Ennis

Location:
United States
Stephen Ennis Photo 48

Stephen Ennis

Location:
United States

Publications & IP owners

Us Patents

Shared Resources In A Chip Multiprocessor

US Patent:
7383423, Jun 3, 2008
Filed:
Oct 1, 2004
Appl. No.:
10/957250
Inventors:
William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Philip E. Madrid - Austin TX, US
Stephen C. Ennis - Austin TX, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 15/00
US Classification:
712 28
Abstract:
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e. g. a chip multiprocessor).

Shared Resources In A Chip Multiprocessor

US Patent:
7840780, Nov 23, 2010
Filed:
Apr 4, 2008
Appl. No.:
12/098303
Inventors:
William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Philip E. Madrid - Austin TX, US
Stephen C. Ennis - Austin TX, US
Assignee:
Globalfoundries Inc. - Grand Cayman
International Classification:
G06F 9/00
US Classification:
712 30, 712 28
Abstract:
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e. g. a chip multiprocessor).

Shared Resources In A Chip Multiprocessor

US Patent:
7996653, Aug 9, 2011
Filed:
Oct 7, 2010
Appl. No.:
12/899979
Inventors:
William A. Hughes - San Jose CA, US
Kiran K. Bondalapati - Los Altos CA, US
Philip E. Madrid - Austin TX, US
Stephen C. Ennis - Austin TX, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
G06F 9/30
US Classification:
712 28
Abstract:
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, dependent on which processor core transmitted the first read operation. In another embodiment, the node comprises the processor cores and the node controller. The node controller comprises a queue shared by the processor cores. The processor cores are configured to transmit communications at a maximum rate of one every N clock cycles, where N is an integer equal to a number of the processor cores. In still another embodiment, a node comprises the processor cores and a plurality of fuses shared by the processor cores. In some embodiments, the node components are integrated onto a single integrated circuit chip (e. g. a chip multiprocessor).

Housing For Electrical Equipment

US Patent:
D318874, Aug 6, 1991
Filed:
Jul 11, 1989
Appl. No.:
7/378812
Inventors:
Floyd J. Pushelberg - Ottawa, CA
Stephen R. Ennis - Fremont CA
Stanley W. Heldenbrand - San Jose CA
Howard R. Cederberg - Danville CA
Assignee:
Northern Telecom Limited - Montreal
US Classification:
D14240

Possible Relatives

Cynthia Ennis  David F Ennis  Dawn E Ennis  Debbie L Ennis  Deborah A Ennis  Dana L Ennis  Daniel A Ennis  Stephen H Last  Stephen V Johnson  Stephen Stamps 

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