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Stephen E Sox, 59460 Oliveta Pl, La Canada, CA 91011

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460 Oliveta Pl, La Canada Flintridge, CA 91011    818-9522794   

4405 El Camino Corto, La Canada Flintridge, CA 91011    818-9522794   

La Canada, CA   

7738 Jeanie Ter, Tujunga, CA 91042    818-3527923   

La Crescenta, CA   

Woodland Hills, CA   

Los Altos, CA   

La Canada Flt, CA   

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Us Patents

Stacked Integrated Circuit Assembly

US Patent:
7888176, Feb 15, 2011
Filed:
Sep 10, 2009
Appl. No.:
12/557205
Inventors:
Tse E. Wong - Los Alamitos CA, US
Samuel D. Tonomura - Rancho Palos Verdes CA, US
Stephen E. Sox - La Canada CA, US
Timothy E. Dearden - Torrance CA, US
Clifton Quan - Arcadia CA, US
Polwin C. Chan - Monterey Park CA, US
Mark S. Hauhe - Hermosa Beach CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H01L 21/00
US Classification:
438108, 438113, 438116, 438123, 257E21503, 257E23069, 257E23144, 257E23153
Abstract:
In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Stacked Integrated Circuit Assembly

US Patent:
2008017, Jul 31, 2008
Filed:
Jan 25, 2007
Appl. No.:
11/698602
Inventors:
Tse E. Wong - Los Alamitos CA, US
Samuel D. Tonomura - Rancho Palos Verdes CA, US
Stephen E. Sox - La Canada CA, US
Timothy E. Dearden - Torrance CA, US
Clifton Quan - Arcadia CA, US
Polwin C. Chan - Monterey Park CA, US
Mark S. Hauhe - Hermosa Beach CA, US
International Classification:
H01L 23/538
H01L 27/14
H01L 21/70
US Classification:
257778, 257428, 438460, 438 68, 257E23169, 257E27122, 257E21532
Abstract:
A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

Fastener With Bilateral Seal For Liquid Immersion Cooling Applications

US Patent:
2009026, Oct 29, 2009
Filed:
Apr 29, 2008
Appl. No.:
12/150568
Inventors:
Ethan S. Heinrich - San Pedro CA, US
Alberto F. Viscarra - Torrance CA, US
Jennifer G. Wensel - Redondo Beach CA, US
Stephen E. Sox - La Canada CA, US
International Classification:
F16B 33/00
F16B 43/00
US Classification:
411369, 4113711
Abstract:
A fastener assembly including an elongate fastener adapted to extend through a chamber having a longitudinal axis, a first end and a second end; a first seal disposed at least partially at the first end of the fastener to prevent leakage of fluid from the chamber; and a second seal disposed at least partially at the second end of the fastener to prevent leakage of fluid from the chamber. In a specific embodiment, the first and second seals are conical seals and a third seal is provided by a gasket. The invention also provides a method for securing a fluid filled chamber to a surface comprising the steps of: placing an insert onto the surface such that a first end of the insert abuts the surface; placing the chamber onto the surface whereby the insert extends through an opening therethrough; threading a first end of a threaded fastener through the insert into the surface thereby closing a first lower seal arrangement; and securing the chamber to the surface by sealing the chamber with a nut thereby closing a second seal arrangement with respect to the chamber.

Hybrid Micro-Circuit Device With Stacked Chip Components

US Patent:
2018012, May 3, 2018
Filed:
Oct 31, 2016
Appl. No.:
15/339208
Inventors:
- Waltham MA, US
Samuel D. Tonomura - Rancho Palos Verdes CA, US
Stephen E. Sox - La Canada CA, US
International Classification:
H01L 25/065
H01L 23/31
H01L 23/367
H01L 29/161
H01L 29/20
Abstract:
A hybrid micro-circuit device has multiple layers overlying a printed circuit board (PCB), including a first semiconductor chip component that is electrically connected to the PCB, and a second semiconductor chip component that is electrically connected to first semiconductor chip component. A molding compound surrounds the stack of components that includes the semiconductor chip components. This molding compound may include pillars that are higher than the height of the stacked components. The pillars of molded material may be configured to receive most of the stress from other components over the stacked components. The pillars of molded material may also help define a recess between the stack components and the other components that overlie the stacked components, where a thermal interface material (TIM) may be located. Further, there may be an air gap between parts of the semiconductor chip components.

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