Stephen G Strickland, 6826 Heyward Hills Dr, Holmdel Village, NJ 07733

6501733, Dec 31, 2002

Oct 1, 1999

09/411007

Steven Anthony Falco - Morris Plains NJ
Stephen Gregory Strickland - Holmdel NJ
Ming-Hsu Tu - Somerset NJ

Lucent Technologies Inc. - Murray Hill NJ

G01R 3108

370235, 370429, 37926601

A communications node predicts a transmission-departure time of a receive data message from an output upon reception of the receive data message at an input of the communications node. The communications node determines if the receive data message would remain stored within the communications node for a latent duration longer than a waiting-time limit based on the predicted transmission-departure time. The communications node admits the receive data message, for storage in a buffer memory of the communications node for prospective transmission over the output, if the receive data message would be transmitted prior to expiration of the waiting-time limit.

6545996, Apr 8, 2003

Dec 10, 1998

09/209509

Steven Anthony Falco - Morris Plains NJ
Stephen Gregory Strickland - Holmdel NJ
Ming-Hsu Tu - Somerset NJ

Lucent Technologies Inc. - Murray Hill NJ

H04Q 100

370347, 455515

A method that selects one of a plurality of priority schemes for scheduling messages for one of cyclically repeating sets of time slots of a control channel based on at least one of a plurality of characteristics of the state of the control channel. The state of the control channel is all information regarding what has arrived, what is queued, and what has been transmitted. This includes the status of the queues, the messages awaiting transmission, along with their type and the time they have been waiting, the sequence of past transmissions, as well as other information.

6700869, Mar 2, 2004

Oct 1, 1999

09/410615

Steven Anthony Falco - Morris Plains NJ
Stephen Gregory Strickland - Holmdel NJ
Ming-Hsu Tu - Somerset NJ

Lucent Technologies Inc. - Murray Hill NJ

H04L 1256

370230, 370412, 370428

A communications node admits the receive data message to the buffer memory if the receive arriving message falls within the capacity range of a class of the receive data messages and if the buffer memory is not congested. A state detector detects if the buffer memory is congested by evaluating the occupancy rate of the buffer memory, or otherwise. The capacity range determines the utilization of buffer memory by a particular class of data messages, which may be defined in accordance with an estimated economic value rating of the data messages.

6924986, Aug 2, 2005

Jun 27, 2003

10/608745

Steven D. Sardella - Marlborough MA, US
Stephen E. Strickland - Marlborough MA, US
Bassem N. Bishay - Attleboro MA, US

EMC Corporation - Hopkinton MA

H05K007/10

361785, 361788, 439 65, 439218

Disclosed is a system including a circuit board and several pluggable modules coupled to the circuit board. The several pluggable modules are insertable through side-by-side slots in an enclosure in which the circuit board resides. A first pluggable module is coupled to the circuit board via a first connector, while a second pluggable module is coupled to the circuit board via a second connector such that the second pluggable module is laterally offset from the first pluggable module. The first and second connectors are right angle connectors, and the second right angle connector is inverted relative to the first right angle connector. The first and second pluggable modules are I/O modules for transporting high speed differential signals, and wherein the first pluggable module includes several XFP connectors, and wherein the second pluggable module includes several SFP connectors. The second pluggable module includes several SFP connectors arranged on both sides of the pluggable module.

7154723, Dec 26, 2006

Jun 27, 2003

10/608635

Bernard Warnakulasooriya - Franklin MA, US
Steven D. Sardella - Marlborough MA, US
Mickey Steven Felton - Sterling MA, US
Stephen E. Strickland - Marlborough MA, US
Phillip Roux - Sutton MA, US

EMC Corporation - Hopkinton MA

H02H 3/00

361 62, 361103

In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are coupled to both of the first and second serial bus controllers on each of the first and second controller boards. The first serial bus is coupled to the first power supply, while the second serial bus coupled to the second power supply. The first and second serial buses are used for exchanging enclosure management and environmental information between the first and second power supplies and the first and second controller boards. The first and second serial buses are coupled to isolation switches so that redundant modules can operate if a serial bus controller fails.

7254016, Aug 7, 2007

May 25, 2004

10/853746

Stephen E. Strickland - Marlboro MA, US
Adrianna D. Bailey - Upton MA, US
Steven D. Sardella - Marlborough MA, US
Alan McIlvene - Shrewsbury MA, US
Maida Boudreau - Brimfield MA, US

EMC Corporation - Hopkinton MA

H05K 5/00
H05K 7/00

361684, 439 61, 361788, 361724

A data storage system having an interconnect, storage devices coupled to a first side of the interconnect, and a processing subsystem coupled to a second side of the interconnect that is substantially opposite the first side. The method involves a user (e. g. , a customer) receiving a fault signal from the data storage system (e. g. , an email notification, a GUI message, an LED pattern, etc. ), identifying a component of the data storage system as faulty in response to receiving the fault signal, and replacing the identified component with a new component. In general, the user replaces the identified component in a hot-swapping manner when the identified component is a storage device or a power supply. Additionally, the user replaces the identified component in a powered-down manner when the identified component is a portion of a storage processing circuit (e. g. , an internal fan, a memory circuit, a storage processing circuit, etc. ).

7279856, Oct 9, 2007

Mar 31, 2006

11/395460

Douglas Sullivan - Hopkinton MA, US
Stephen Strickland - Marlboro MA, US
Michael J. Kozel - Upton MA, US

EMC Corporation - Hopkinton MA

H02P 7/08

318 66, 318560, 318568, 307 64, 701301, 701306, 361 30

A hot-pluggable I/O annex module of a storage processor assembly includes interface circuitry providing connections to an optional I/O interface module. The I/O annex module includes redundant cooling fans providing cooling airflow to an I/O annex mounting area, main power conversion circuitry for generating main operating power for the interface circuitry, auxiliary power conversion circuitry for generating auxiliary power, a controller for monitoring and controlling the operation of cooling fans; and monitoring circuitry powered by the auxiliary power for monitoring correct operation of the controller and, upon detecting incorrect operation, disabling the main power conversion circuitry. The monitoring circuitry includes a watchdog timer and a latch collectively operative to (i) determine if a controller status signal indicating correct operation of the controller does not toggle for a watch interval, and if so then (ii) enter an operating state in which the main power conversion circuitry is disabled and cannot be re-enabled except by cycling the primary power or removing and reinserting the I/O annex module to/from the storage processor assembly.

7281150, Oct 9, 2007

Mar 26, 2004

10/810431

Stephen Strickland - Marlboro MA, US

EMC Corporation - Hopkinton MA

G06F 1/00

713330, 713300, 713310, 713340, 327142, 327143, 327198

A data storage system includes power circuitry configured to provide power signals, storage processing circuitry configured to perform data storage operations, and a packaged microcontroller coupled to the power circuitry and the storage processing circuitry. The packaged microcontroller has input lines, output lines, and control circuitry coupled to the input lines and the output lines. The control circuitry is configured to (i) receive, on the input lines, first power signals (e. g. , voltage signals for I/O circuitry) which is provided by the power circuitry to the storage processing circuitry, (ii) wait a predetermined time period in response to receipt of the first power signals on the input lines, and (iii) output, through the output lines, enable signals to the power circuitry after waiting the predetermined time period. The enable signals directs the power circuitry to provide second power signals to the storage processing circuitry (e. g. , voltage signals for core circuitry).