Steve Joy resumes & CV records
Resumes
Steve Joy
Steve Joy
Work:
Web Printing
Steve Grayce Joy
Steve M Joy, 67Belmont, ME
Steve Joy Phones & Addresses
Morrill, ME
Searsmont, ME
3325 131St Ave, Portland, OR 97229 503-6171431
Mentions for Steve M Joy
Publications & IP owners
Us Patents
Apparatus And Method For Improving Circuit Board Solder
US Patent:
6429383, Aug 6, 2002
Filed:
Apr 14, 1999
Appl. No.:
09/291724
Inventors:
John T. Sprietsma - Hillsboro OR
Steve Joy - Portland OR
Bryce Horine - Aloha OR
Steve Joy - Portland OR
Bryce Horine - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 116
US Classification:
174260, 174261, 29852, 257698, 361807
Abstract:
A circuit board includes electrical interconnect mounting pads for mounting electronic devices thereto. Some of the electrical interconnect mounting pads include a plated through hole which traverses through the circuit board. One end of the plated through holes is closed, plugged or covered to prevent migration of solder through the plated through holes during a solder operation. The reduction in solder migration, as a result of plugging the plated through hole, increases solder joint quality over solder joint quality achieved using plated through holes which are not closed at one end.
Multiple Layer Printed Circuit Board Having Power Planes On Outer Layers
US Patent:
6288906, Sep 11, 2001
Filed:
Dec 18, 1998
Appl. No.:
9/216780
Inventors:
John T. Sprietsma - Hillsboro OR
Steve Joy - Portland OR
Steve Joy - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01R 900
US Classification:
361772
Abstract:
A multi-layer printed circuit board includes power planes located on outer conductive layers. The outer conductive layers are patterned to accept circuitry, such as integrated circuits and surface mount devices. Mounting pads are provided on the outer conductive layers which include plated through vias for electrical interconnection with other conductive layers of the printed circuit board. To increase solderability, the plated through vias are located on the mounting pads such that they are covered by the circuit component mounted thereto. By locating the vias under the electrical components, such as surface mount capacitors, the quality of solder fillets is increased. To enhance heat dissipation, openings are provided in solder masks located on exterior surfaces of the outer conductive planes. These openings are located in the solder mask to expose the conductive plane. As such, the openings are located in areas where circuitry is not mounted to the printed circuit board.
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