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Steven Michael Baier, 6417490 Blue Jay Dr, Morgan Hill, CA 95037

Known as:
Steven M Baier Sm Baier Steve M Baier
Related to:
Pamela Jane Baier 66

Steven Baier Phones & Addresses

17490 Blue Jay Dr, Morgan Hill, CA 95037    408-6128586   

Richfield, MN   

San Jose, CA   

15381 Highland Rd, Minnetonka, MN 55345    952-9880842   

Santa Clara, CA   

17490 Blue Jay Dr, Morgan Hill, CA 95037    408-6774274   

Work

Company: Goodwill industries - Shamokin Dam, PA Feb 2012 Position: Production associate -temporary

Education

School / High School: Gallaudet University- Washington, DC May 2005 Specialities: Bachelor of Science in Computer Information Systems

Skills

Computer Operator • Computer Laser Printer • Database administrator.
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Steven Baier resumes & CV records

Resumes

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Steven Baier

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Steven Baier

Steven Baier Photo 28

Steven Baier - Williamsport, PA

Work:
Goodwill Industries - Shamokin Dam, PA Feb 2012 to Feb 2012
Production Associate -Temporary Self employed - Williamsport, PA Jan 2008 to Jan 2012
Elder home care Bender Consulting Group - Pittsburgh, PA Apr 2007 to Dec 2007
IT Specialist -Contract Defense Logistics Agency - New Cumberland, PA May 2006 to Oct 2006
IT Specialist - Internship Gallaudet University - Washington, DC Jan 2002 to Dec 2005
Computer Lab Proctor Educational Credit Management Corporation - Saint Paul, MN Jun 2005 to Aug 2005
Internship PA Department of Public Welfare - Harrisburg, PA Jul 1998 to Dec 1999
Computer Operator Computer Lab Proctor - Rochester, NY Mar 1994 to Feb 1995
Student Position Part-Time Chemical Banking Corporation - Rochester, NY Feb 1988 to Mar 1994
Senior Computer Operator, Full-Time IMPCO - Rochester, NY Sep 1992 to Oct 1992
Computer Operator, Temporary Part-Time
Education:
Gallaudet University - Washington, DC May 2005
Bachelor of Science in Computer Information Systems NTID/ Rochester Institute of Technology - Rochester, NY Nov 1994
A.A.S. Fairport High School - Fairport, NY Jun 1981
Diploma in General Education
Skills:
Computer Operator, Computer Laser Printer, Database administrator.

Publications & IP owners

Us Patents

Optoelectronic Devices And Method Of Production

US Patent:
6724798, Apr 20, 2004
Filed:
Dec 31, 2001
Appl. No.:
10/037013
Inventors:
Yue Liu - Plymouth MN
Klein L. Johnson - St. Paul MN
Steven M. Baier - Minnetonka MN
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01S 5183
US Classification:
372 96, 257446, 257466, 257499, 372 50
Abstract:
The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

High Speed Serial I/O Technology Using An Optical Link

US Patent:
6821029, Nov 23, 2004
Filed:
Sep 10, 2002
Appl. No.:
10/241289
Inventors:
Bernard L. Grung - Eden Prairie MN
Wayne L. Walters - Prior Lake MN
Steven M. Baier - Minnetonka MN
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G02B 636
US Classification:
385 92, 385 88, 438 31, 438 32, 398 22, 398140, 398141
Abstract:
A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

High Speed Serial I/O Technology Using An Optical Link

US Patent:
7044658, May 16, 2006
Filed:
Jul 23, 2004
Appl. No.:
10/897541
Inventors:
Bernard L. Grung - Eden Prairie MN, US
Wayne L. Walters - Prior Lake MN, US
Steven M. Baier - Minnetonka MN, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G02B 6/36
H04B 17/00
H01L 21/00
US Classification:
385 92, 385 88, 438 31, 438 32, 398 22, 398140, 398141
Abstract:
A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

Optoelectronic Devices And Methods Of Production

US Patent:
7151785, Dec 19, 2006
Filed:
Sep 24, 2003
Appl. No.:
10/669220
Inventors:
Yue Liu - Plymouth MN, US
Klein L. Johnson - St. Paul MN, US
Steven M. Baier - Minnetonka MN, US
Assignee:
Finisar Corporation - Sunnyvale CA
International Classification:
H01S 5/00
US Classification:
372 4401, 372 501
Abstract:
The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Integrated Capacitor With Alternating Layered Segments

US Patent:
7944732, May 17, 2011
Filed:
Nov 21, 2008
Appl. No.:
12/276280
Inventors:
Jan Lodewijk de Jong - Cupertino CA, US
Steven Baier - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 11/24
G11C 5/02
G11C 5/06
US Classification:
365149, 365 51, 365 63, 257208, 257532, 257E2707, 257E29343
Abstract:
A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link.

Gated Transmission Line Model Structure For Characterization Of Field-Effect Transistors

US Patent:
4638341, Jan 20, 1987
Filed:
Sep 6, 1984
Appl. No.:
6/647769
Inventors:
Steven M. Baier - Minneapolis MN
Nicholas C. Cirillo - Minneapolis MN
Steven A. Hanka - Minneapolis MN
Michael S. Shur - Golden Valley MN
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
H01L 2948
H01L 2956
H01L 2964
US Classification:
357 15
Abstract:
The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET's. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels.

Possible Relatives

Cynthia Baier  David L Baier  Daniel Baier  Denise M Baier  Dennis W Baier  Darrell S Baier  Dexter E Baier  Steven D Johnson  Steven B Standiford  Steven B Standley 

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