Steven Michael Baier, 6417490 Blue Jay Dr, Morgan Hill, CA 95037

6724798, Apr 20, 2004

Dec 31, 2001

10/037013

Yue Liu - Plymouth MN
Klein L. Johnson - St. Paul MN
Steven M. Baier - Minnetonka MN

Honeywell International Inc. - Morristown NJ

H01S 5183

372 96, 257446, 257466, 257499, 372 50

The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

6821029, Nov 23, 2004

Sep 10, 2002

10/241289

Bernard L. Grung - Eden Prairie MN
Wayne L. Walters - Prior Lake MN
Steven M. Baier - Minnetonka MN

Xilinx, Inc. - San Jose CA

G02B 636

385 92, 385 88, 438 31, 438 32, 398 22, 398140, 398141

A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

7044658, May 16, 2006

Jul 23, 2004

10/897541

Bernard L. Grung - Eden Prairie MN, US
Wayne L. Walters - Prior Lake MN, US
Steven M. Baier - Minnetonka MN, US

Xilinx, Inc. - San Jose CA

G02B 6/36
H04B 17/00
H01L 21/00

385 92, 385 88, 438 31, 438 32, 398 22, 398140, 398141

A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

7151785, Dec 19, 2006

Sep 24, 2003

10/669220

Yue Liu - Plymouth MN, US
Klein L. Johnson - St. Paul MN, US
Steven M. Baier - Minnetonka MN, US

Finisar Corporation - Sunnyvale CA

H01S 5/00

372 4401, 372 501

The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

7944732, May 17, 2011

Nov 21, 2008

12/276280

Jan Lodewijk de Jong - Cupertino CA, US
Steven Baier - San Jose CA, US

Xilinx, Inc. - San Jose CA

G11C 11/24
G11C 5/02
G11C 5/06

365149, 365 51, 365 63, 257208, 257532, 257E2707, 257E29343

A capacitor in an integrated circuit (“IC”) has a first node plate link formed in a first metal layer of the IC electrically connected to and forming a portion of a first node of the capacitor extending along a first axis (y) and a second node plate link formed in a second metal layer of the IC extending along the axis and connected to the first node plate with a via. A third node plate link formed in the first metal layer is electrically connected to and forming a portion of a second node of the capacitor and extends along a second axis (x) of the node plate array transverse to the first node plate link, proximate to an end of the first node plate link and overlying a portion of the second node plate link.

4638341, Jan 20, 1987

Sep 6, 1984

6/647769

Steven M. Baier - Minneapolis MN
Nicholas C. Cirillo - Minneapolis MN
Steven A. Hanka - Minneapolis MN
Michael S. Shur - Golden Valley MN

Honeywell Inc. - Minneapolis MN

H01L 2948
H01L 2956
H01L 2964

357 15

The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET's. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels.