Steven Bucher, 6611343 Old Bren Rd, Hopkins, MN 55343

6393587, May 21, 2002

May 3, 2001

09/848128

Steven Bucher - Minnetonka MN
Daniel G. Kuechle - Ramsey MN
Timothy A. Wall - Big Lake MN

I-TECH Corporation - Eden Prairie MN

G06F 1125

714 39, 714 45, 714712

A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

6507923, Jan 14, 2003

Apr 19, 1999

09/294935

Timothy A. Wall - Big Lake MN
Eric D. Seppanen - Brooklyn Center MN
Steven Bucher - Minnetonka MN
Daniel G. Kuechle - Ramsey MN

I-Tech Corporation - Minneapolis MN

G01R 3128

714712, 714821

An integrated multi-channel Fiber Channel analyzer provides coordinated and cooperative triggering and capture of data across multiple channels in a Fiber Channel network. The integrated multi-channel analyzer accommodates up to sixteen separate analyzer channels in a single cabinet. Each analyzer channel is comprised of an input port connection to the Fiber Channel network, a trace buffer memory that captures data and logic circuitry that controls the operation of the trace buffer memory in response to a status condition. A high speed status bus is connected to each analyzer channel and propagates the status conditions of each analyzer channel to all other analyzer channels. In this way, the integrated multi-channel analyzer allows for distributive control over triggering decisions across multiple analyzer channels, and also allows for multi-level triggering where different conditions may be detected by different analyzer channels. Analysis of the data captured by the integrated multi-channel analyzer is further enhanced by a processor resident in the cabinet that is connected by a data/control bus to each analyzer channel and by a hardware search engine associated with each trace buffer memory. The resident processor receives high level commands from a remote host processor and sends selected trace data to the remote host computer over an Ethernet connection.

6915466, Jul 5, 2005

May 7, 2001

09/850673

Jeff Mastro - Anoka MN, US
Steven Bucher - Minnetonka MN, US

I-Tech Corp. - Eden Prairie MN

G01R031/28

714712, 714821

Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions. Each analyzer channel includes an input connection port, a trace buffer memory and logic circuitry. Each input connection port is operably connected to a unique node in the communication network. A host processor connected to each analyzer channel assigns ownership of a unique set of analyzer channel to at least two different users such that each user can initiate separate traces that are simultaneously established on the connection port at each node in accordance with a set of instructions established by the user assigned to the analyzer channel for that node, and the traces are captured in response to the set of instructions for each analyzer channel such that each user retrieves only the results of the analyzer channels assigned to that user.

7398437, Jul 8, 2008

Apr 26, 2005

11/114265

Jeff Mastro - Anoka MN, US
Steven Bucher - Minnetonka MN, US

Finisar Corporation - Sunnyvale CA

G01R 31/28

714712, 714717, 714821

Multiple channels of a multi-channel analyzer are allocated among multiple users such that each user can initiate and retrieve the results of separate diagnostic sessions or strategies. Each analyzer channel includes an input connection port, a trace buffer memory and logic circuitry. The input connection port is operably connected to a unique node in the communication network. A host processor assigns ownership of a unique set of analyzer channels to at least two users such that each user can initiate separate simultaneously established traces on the communication network. The logic circuitry monitors frame data on the connection port at each node in accordance with a set of instructions established by the user assigned to the analyzer channel for that node, and the traces are captured in response to the set of instructions such that each user retrieves only results of the analyzer channels assigned to that user.

D345961, Apr 12, 1994

Nov 12, 1992

D/001376

Steven Bucher - Minnetonka MN
Wayne A. Kosters - Eden Prairie MN

I-Tech Corp - Eden Prairie MN

D13147

5715409, Feb 3, 1998

May 24, 1993

8/067473

Steven Bucher - Minnetonka MN
Wayne A. Kosters - Eden Prairie MN

I-Tech Corporation - Edina MN

G06F 1314

395309

A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers. The receivers and transceivers present an appropriate set of TTL signals to a SCSI device that have values which correspond to the proper value of the electrical signals on the SCSI bus, regardless of whether the SCSI bus is configured to use the single-ended protocol or the differential protocol. In a preferred embodiment, a single universal SCSI connector detachably connects to and receives and/or transmits electrical signals from a SCSI bus configured to use either the single-ended or differential parallel interface protocols.

5671376, Sep 23, 1997

May 7, 1996

8/646080

Steven Bucher - Minnetonka MN
Wayne A. Kosters - Eden Prairie MN

I-Tech Corporation - Edina MN

G06F 1314

395309

A universal electrical interface system connects to a small computer system interface (SCSI) bus. In a passive embodiment, a set of single-ended receivers and a set of differential receivers receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of receivers is enabled. In an active embodiment, a set of single-ended transceivers and a set of differential transceivers transmit and receive electrical signals on the SCSI bus according to the single-ended or differential protocol, respectively, when each set of transceivers is enabled. A control mechanism connected to both sets of receivers or transceivers automatically determines whether the SCSI bus is configured to use either the single-ended or differential parallel interface protocol and selectively enables the set of single ended receivers or transceivers, or the set of differential receivers or transceivers. The receivers and transceivers present an appropriate set of TTL signals to a SCSI device that have values which correspond to the proper value of the electrical signals on the SCSI bus, regardless of whether the SCSI bus is configured to use the single-ended protocol or the differential protocol. In a preferred embodiment, a single universal SCSI connector detachably connects to and receives and/or transmits electrical signals from a SCSI bus configured to use either the single-ended or differential parallel interface protocols.

6266789, Jul 24, 2001

Nov 17, 1998

9/193779

Steven Bucher - Minnetonka MN
Daniel G. Kuechle - Ramsey MN
Timothy A. Wall - Big Lake MN

I-Tech Corporation - Eden Prairie MN

G06F 1125

714 39

A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.