Steven Michael Farrer, 64525 Woodhams Rd, Santa Clara, CA 95051

8111942, Feb 7, 2012

Feb 6, 2008

12/012847

Steven M. Farrer - Santa Clara CA, US
Neil Morrow - San Jose CA, US

O2Micro, Inc. - Santa Clara CA

G06K 9/40

382274, 382181, 382209

There is provided an electronic system including an image capturing device and a comparator coupled to the image capturing device. The image capturing device is operable for capturing a live image. The comparator generates a feedback signal by comparing the live image with a reference image and adjusts at least one setting of the image capturing device by the feedback signal.

8417054, Apr 9, 2013

Jan 6, 2012

13/345618

Steven M. Farrer - Santa Clara CA, US
Neil Morrow - McKinney TX, US

O2Micro Inc. - Santa Clara CA

G06K 9/40

382274

There is provided a recognition system. The recognition system is coupled to an image capturing device, and determines a first matching percentage by comparing a first live image with a first reference image, determines a second matching percentage by comparing a second live image with the first reference image, compares the first matching percentage with the second matching percentage to determine a direction of adjustment of a setting of the image capturing device, and generates a feedback signal to adjust the setting based on the direction of adjustment. The first live image and second live image are captured by the image capturing device.

5465367, Nov 7, 1995

Jul 19, 1994

8/277771

Chandrashekar M. Reddy - Santa Clara CA
Scott D. Hirose - San Jose CA
Sung-Soo Cho - Sunnyvale CA
James P. Kardach - San Jose CA
Steven M. Farrer - Santa Clara CA
Meeling Roberts - Fremont CA

Intel Corporation - Santa Clara CA

G06F 132

395750

A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced.

5448717, Sep 5, 1995

Jul 6, 1993

8/088151

Mark J. Balmer - Tigard OR
Steven M. Farrer - Santa Clara CA

Intel Corporation - Santa Clara CA

G06F 104

395550

The invention provides a register, which when set to a specific value, ensures that memory accesses take at least a specified number of clock cycles. The invention specifically introduces delays into the memory accesses when a memory bank control register is configured to operate the memory bank in a fast-CAS (fast column address strobe) mode of operation. The delays are introduced transparent to the values in the memory bank control register that otherwise controls the operation of the memory bank. The delay introduced by the invention permits an in-circuit-emulation (ICE) system sufficient time to transfer trace data from the microprocessor to the ICE-base.

5307320, Apr 26, 1994

Sep 23, 1992

7/949708

Steven M. Farrer - Santa Clara CA
Eugene P. Matter - San Jose CA

Intel Corporation - Santa Clara CA

G11C 800

36523001

A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, the present invention is capable of accommodating DRAM banks of different types in the memory array.