Steven J Hayashi Deceased7144 Martwood Way, San Jose, CA 95120

Steven Hayashi Phones & Addresses

7144 Martwood Way, San Jose, CA 95120 408-9276325

3466 Wine Cask Way, San Jose, CA 95124

Redondo Beach, CA

311 S Lucia Ave, Redondo Beach, CA 90277 760-6415008

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Steven J Hayashi

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: High school graduate or higher

Industries

Computer Software

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Career records & work history

Medicine Doctors

Steven A. Hayashi

Specialties:

Internal Medicine

Work:

Virginia Mason Medical Center Clinic
1100 9 Ave, Seattle, WA 98101
206-6241144 (phone) 206-2236982 (fax)
Site

Education:

Medical School
New York University School of Medicine
Graduated: 1983

Procedures:

Arthrocentesis, Cardiac Stress Test, Destruction of Benign/Premalignant Skin Lesions, Vaccine Administration

Conditions:

Acute Pharyngitis, Acute Upper Respiratory Tract Infections, Anxiety Phobic Disorders, Benign Prostatic Hypertrophy, Contact Dermatitis, Diabetes Mellitus (DM), Disorders of Lipoid Metabolism, Gastroesophageal Reflux Disease (GERD), Hemorrhoids, Hypothyroidism, Ischemic Heart Disease, Osteoarthritis, Abdominal Hernia, Acne, Acute Bronchitis, Acute Sinusitis, Alcohol Dependence, Alopecia Areata, Alzheimer's Disease, Anemia, Anxiety Dissociative and Somatoform Disorders, Atrial Fibrillation and Atrial Flutter, Attention Deficit Disorder (ADD), Bell's Palsy, Benign Paroxysmal Positional Vertigo, Benign Polyps of the Colon, Bipolar Disorder, Bronchial Asthma, Burns, Calculus of the Urinary System, Candidiasis of Vulva and Vagina, Cardiac Arrhythmia, Carpel Tunnel Syndrome, Cholelethiasis or Cholecystitis, Cirrhosis, Constipation, Dementia, Depressive Disorders, Dermatitis, Diverticulitis, Emphysema, Erectile Dysfunction (ED), Esophagitis, Fractures, Dislocations, Derangement, and Sprains, Gastritis and Duodenitis, Gastrointestinal Hemorrhage, Glaucoma, Gout, Hearing Loss, Heart Failure, Herpes Simplex, Herpes Zoster, Hypertension (HTN), Infectious Liver Disease, Inguinal Hernia, Insomnia, Iron Deficiency Anemia, Irritable Bowel Syndrome (IBS), Lateral Epicondylitis, Menopausal and Postmenopausal Disorders, Migraine Headache, Non-Toxic Goiter, Osteoporosis, Otitis Media, Peripheral Nerve Disorders, Phlebitis and Thrombophlebitis, Plantar Fascitis, Plantar Warts, Pneumonia, Psoriasis, Rheumatoid Arthritis, Rosacea, Septicemia, Skin and Subcutaneous Infections, Skin Cancer, Spinal Stenosis, Substance Abuse and/or Dependency, Tempromandibular Joint Disorders (TMJ), Tension Headache, Tinea Pedis, Tinea Unguium, Transient Cerebral Ischemia, Urinary Incontinence, Urinary Tract Infection (UT), Venous Embolism and Thrombosis, Viral Pneumonia, Vitamin D Deficiency

Languages:

English

Description:

Dr. Hayashi graduated from the New York University School of Medicine in 1983. He works in Seattle, WA and specializes in Internal Medicine. Dr. Hayashi is affiliated with Virginia Mason Medical Center.

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Steven Hayashi resumes & CV records

Resumes

Steven Hayashi

Location:

San Francisco, CA

Industry:

Computer Software

Publications & IP owners

Us Patents

Fault-Tolerant Multiprocessor System

US Patent:

4817091, Mar 28, 1989

Filed:

May 19, 1987

Appl. No.:

7/052094

Inventors:

James A. Katzman - San Jose CA
Joel F. Bartlett - Palo Alto CA
Richard M. Bixler - Sunnyvale CA
William H. Davidow - Atherton CA
John A. Despotakis - Pleasanton CA
Peter J. Graziano - Los Altos CA
Michael D. Green - Los Altos CA
David A. Greig - Cupertino CA
Steven J. Hayashi - Cupertino CA
David R. Mackie - Ben Lomond CA
Dennis L. McEvoy - Scotts Valley CA
James G. Treybig - Sunnyvale CA
Steven W. Wierenga - Sunnyvale CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1120

US Classification:

371 9

Abstract:

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

Multiprocessor System

US Patent:

4484275, Nov 20, 1984

Filed:

Jun 17, 1983

Appl. No.:

6/504596

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 304
G06F 1300

US Classification:

364200

Abstract:

An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller. The bit can be reset to prevent that device controller from transmitting spurious signals which could interfere with interrupt requests being transmitted to the channel by other device controllers so that a failed device controller can be effectively removed from the system.

Interprocessor Communication

US Patent:

4807116, Feb 21, 1989

Filed:

May 18, 1987

Appl. No.:

7/052095

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1336
G06F 1342

US Classification:

364200

Abstract:

In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i. e. , busy or available); and the bus controller then signaling transmission commencement.

Multiprocessor System

US Patent:

4356550, Oct 26, 1982

Filed:

May 6, 1980

Appl. No.:

6/147305

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1120

US Classification:

364200

Abstract:

A multiprocessor system, the kind in which two or more separate processor modules are interconnected for two power supplies, provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user program.

Data Error Detection And Device Controller Failure Detection In An Input/Output System

US Patent:

4672537, Jun 9, 1987

Filed:

Apr 29, 1985

Appl. No.:

6/727614

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1110
G06F 1116

US Classification:

364200

Abstract:

A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port. The device controller controls the transfer of information between a processor module and a peripheral device, and information is gated into a register in a port in a device controller in response to a gating signal generated by a processor module. Parity generation and check means continuously monitor parity for the duration of the gating signal.

Multiprocessor System

US Patent:

4672535, Jun 9, 1987

Filed:

Mar 18, 1985

Appl. No.:

6/713583

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300
G06F 1516

US Classification:

364200

Abstract:

In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Multiprocessor System

US Patent:

4228496, Oct 14, 1980

Filed:

Sep 7, 1976

Appl. No.:

5/721043

Inventors:

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1516
G06F 1506

US Classification:

364200

Abstract:

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system.

Multiprocessor System

US Patent:

4365295, Dec 21, 1982

Filed:

May 6, 1980

Appl. No.:

6/147309

Inventors:

James A. Katzman - San Jose CA
Joel F. Bartlett - Palo Alto CA
Richard M. Bixler - Sunnyvale CA
William H. Davidow - Atherton CA
John A. Despotakis - Pleasanton CA
Peter J. Graziano - Los Atlos CA
Michael D. Green - Los Atlos CA
David A. Greig - Cupertino CA
Steven J. Hayashi - Cupertino CA
David R. Mackie - Ben Lomond CA
Dennis L. McEvoy - Scotts Valley CA
James G. Treybig - Sunnyvale CA
Steven W. Wierenga - Sunnyvale CA

Assignee:

Tandem Computers Incorporated - Cupertino CA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs.

Possible Relatives

Cynthia L Hayashi David C Hayashi Dawn P Hayashi Dean A Hayashi Daichi H Hayashi Daisuke Hayashi Denise J Hayashi Steven D Johnson Steven B Standiford Steven B Standley

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