Steven M Spangler, 6912895 Calle De Las Rosas, San Diego, CA 92129

6924812, Aug 2, 2005

Dec 24, 2002

10/328988

Satyaki Koneru - Folsom CA, US
Steven J. Spangler - El Dorado Hills CA, US
Val G. Cook - Shingle Springs CA, US

Intel Corporation - Santa Clara CA

G06T011/40

345552, 345554, 345557, 711118, 711131, 711149

A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

6947054, Sep 20, 2005

Dec 19, 2002

10/326728

Steven J. Spangler - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G09G005/00

345582, 345583, 345587, 345611, 345612, 345613, 382260, 708308

Embodiments of the invention provide an anisotropic filtering configuration where a ratio value is computed as the ratio of the major axis to the minor axis of a pixel projection on a texture map. The number of subpixels generated and sampled is based upon the value of the ratio. For four-way anisotropic filtering, subpixels are generated that move as the computed ratio between the major and minor axis increases. Subpixels may be placed anywhere from 0. 5 to 1. 5 texel distance from the pixel center depending on the computed ratio. The contribution of the subpixels is equally weighted.

7586495, Sep 8, 2009

Dec 29, 2006

11/647720

Prasoonkumar Surti - Folsom CA, US
Hong Jiang - El Dorado Hills CA, US
Steven J. Spangler - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06T 15/00
G06T 15/40
G09G 5/36
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/36

345581, 345422, 345589, 345547, 345549, 382254, 382276

According to some embodiments, systems, methods, apparatus, computer program code and means are provided to set a first depth value associated with a plurality of pixels of a video image comprising a plurality of planes, create a first clear rectangle with respect to the first depth value, color render the pixels that are not associated with the first clear rectangle, and render the plurality of planes.

7830397, Nov 9, 2010

Jul 28, 2009

12/510610

Prasoonkumar Surti - Folsom CA, US
Hong Jiang - El Dorado Hills CA, US
Steven J. Spangler - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06T 15/00
G06T 15/40
G09G 5/36
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/36

345581, 345422, 345589, 345547, 345549, 382254, 382276

According to some embodiments, systems, methods, apparatus, computer program code and means are provided to set a first depth value associated with a plurality of pixels of a video image comprising a plurality of planes, create a first clear rectangle with respect to the first depth value, color render the pixels that are not associated with the first clear rectangle, and render the plurality of planes.

7936359, May 3, 2011

Mar 13, 2006

11/375174

Steven J. Spangler - El Dorado Hills CA, US
Benjamin R. Pletcher - Mather CA, US

Intel Corporation - Santa Clara CA

G09G 5/00

345606, 345582, 345586, 345592, 345608, 345609, 345610, 382260, 382300, 382304

A reconfigurable floating point data filter may be implemented by configuring a texture filter in response to state data, where the state data specifying at least a data width of input texture data to be filtered, where the input texture data is in a floating point format, filtering the input texture data using the texture filter, and then reconfiguring the texture filter to be substantially fully utilized when the data width of the input texture data changes.

7975272, Jul 5, 2011

Dec 30, 2006

11/647608

Hong Jiang - El Dorado Hills CA, US
Thomas A. Piazza - Granite Bay CA, US
Brian D. Rauchfuss - Folsom CA, US
Sreedevi Chalasani - San Francisco CA, US
Steven J. Spangler - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06F 9/46
G06F 15/00

718106, 718102, 712216, 712217, 712225

In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.

8544019, Sep 24, 2013

May 26, 2011

13/116245

Hong Jiang - El Dorado Hills CA, US
Thomas A. Piazza - Granite Bay CA, US
Brian D. Rauchfuss - Folsom CA, US
Sreedevi Chalasani - San Francisco CA, US
Steven J. Spangler - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06F 9/46
G06F 15/00

718106, 718102, 712216, 712217, 712225

In some embodiments, a method includes receiving a request to generate a thread and supplying a request to a queue in response at least to the received request. The method may further include fetching a plurality of instructions in response at least in part to the request supplied to the queue and executing at least one of the plurality of instructions. In some embodiments, an apparatus includes a storage medium having stored therein instructions that when executed by a machine result in the method. In some embodiments, an apparatus includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request. In some embodiments, a system includes circuitry to receive a request to generate a thread and to queue a request to generate a thread in response at least to the received request, and a memory unit to store at least one instruction for the thread.

8207978, Jun 26, 2012

Jun 29, 2006

11/478796

Steven J. Spangler - El Dorado Hills CA, US
Benjamin R. Fletcher - Mather CA, US

Intel Corporation - Santa Clara CA

G06T 11/40

345552, 345581, 345582, 345564

Apparatus, systems and methods for the simplification of 3D texture address computations based on aligned, non-perspective objects are disclosed. For example, a method is disclosed including receiving a texture address of a first pixel and determining a texture address of a second pixel by applying at least one offset to the texture address of the first pixel. Other implementations are also disclosed.