Steven B Teig, 40West Sacramento, CA

6516455, Feb 4, 2003

May 10, 2001

09/854182

Steven Teig - Menlo Park CA
Joseph L. Ganley - Vienna VA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 7, 716 9, 716 10

Some embodiments of the invention are placers that use diagonal lines in calculating the cost of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations. For instance, some placers use diagonal lines as cut lines that divide the IC layout into regions.

6526555, Feb 25, 2003

Oct 5, 2001

09/972556

Steven Teig - Menlo Park CA
Andrew Caldwell - Santa Clara CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 11, 716 12, 716 13, 716 14

The present invention introduces methods for implementing gridless non Manhattan architecture for integrated circuits. In one particular embodiment, an integrated circuit layout containing horizontal, vertical, and diagonal interconnect lines is first created. Next, the integrated circuit layout is then compacted. The compacting method first creates groups of horizontal and diagonal interconnect lines sorted by vertical position and groups of vertical and diagonal interconnect lines sorted by horizontal position. The two groups are then compacted in a manner that ensures that a minimum manufacturing line spacing requirement is satisfied.

6581198, Jun 17, 2003

Jun 13, 2001

09/681830

Steven Teig - Menlo Park CA
Arindam Chatterjee - San Carlos CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 10

The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is generally proportional to the length of the approximated section. The capacitance affect from the approximated Manhattan wiring section is then adjusted with a correction factor. Specifically, the present invention proposes that the capacitance be calculated for an interconnect wiring section by multiplying the length of the interconnect wiring section by an approximated capacitance per unit length value of a similar Manhattan wiring segment and adding a correction factor that corrects for the difference between the approximated Manhattan wiring section and the original non Manhattan wiring section.

6618849, Sep 9, 2003

Jan 13, 2002

10/048000

Steven Teig - Menlo Park CA
Heng-Yi Chao - San Jose CA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 12, 716 13

Some embodiments of the invention provide a method that identifies a set of routes for a net that has a set of pins in a region of a design layout. The method initially partitions the region into a number of sub-regions. It then identifies a first set of sub-regions that contains the nets pins. The method next determines whether a storage structure stores a set of routes for the identified first set of sub-regions. If so, the method retrieves the set of routes. If not, the method generates a set of routes. In some embodiments, the method generates a set of routes by first identifying a connection set of sub-regions that when combined with the first set forms a closed set of sub-regions. The closed set of sub-regions does not have any sub-region that is not adjacent to another sub-region in the closed set. The storage structure stores a set of routes for the closed set. For the first set, the method then retrieves the set of routes that are stored for the closed set of sub-regions from the storage structure.

6625611, Sep 23, 2003

Mar 15, 2000

09/526266

Steven Teig - Palo Alto CA
Tom Kronmiller - Chapel Hill NC
Andrew F. Siegel - Shoreline WA

Cadence Design Systems, Inc. - San Jose CA

G06F 1730

707102, 716 17

The mechanism is directed towards method and apparatus for representing multidimensional data. Some embodiments of the invention provide a two-layered data structure to store multidimensional data tuples that are defined in a multidimensional data space. These embodiments initially divide the multidimensional data space into a number of data regions, and create a data structure to represent this division. For each data region, these embodiments then create a hierarchical data structure to store the data tuples within each region. In some of these embodiments, the multidimensional data tuples are spatial data tuples that represent spatial or geometric objects, such as points, lines, polygons, regions, surfaces, volumes, etc. For instance, some embodiments use the two-layered data structure of the invention to store data relating to geometric objects (such as rectangles) that represent interconnect lines of an IC in an IC design layout.

6651233, Nov 18, 2003

Dec 19, 2000

09/745067

Steven Teig - Menlo Park CA
Joseph L. Ganley - Herndon VA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 7, 716 8, 716 9, 716 12, 716 1

One embodiment of the invention is a recursive partitioning method that place circuit elements in an IC layout. This method initially defines a number of partitioning lines that divide an IC region into several sub-regions (also called slots) for a net in the region, the method then identifies the set of sub-regions (i. e. , the set slots) that contain the circuit elements (e. g. , the pins or circuit modules) of that net. The set of sub-regions for the net represents the nets configuration with respect to the defined partitioning lines. Next, the placement method identifies attribute or attributes of a connection graph that models the nets configuration with respect to the partitioning lines. The connection graph for each net provides a topology of interconnect lines that connect the slots that contain the nets circuit elements. According to some embodiments of the invention, the connection graph for each net can have edges that are completely or partially diagonal.

6671864, Dec 30, 2003

Dec 13, 2000

09/737210

Steven Teig - Menlo Park CA
Joseph L. Ganley - Vienna VA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 8, 716 9, 716121

The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

6678872, Jan 13, 2004

Dec 13, 2000

09/737220

Steven Teig - Menlo Park CA
Joseph L. Ganley - Vienna VA

Cadence Design Systems, Inc. - San Jose CA

G06F 1750

716 7, 716 10, 716 11

The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.