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Stuart L Litwin, 661103 Oaklands Dr, Round Rock, TX 78681

Known as:
Stuart Lee Litwin
Related to:
Tamara R Litwin Melissa K Carpenter 39

Stuart Litwin Phones & Addresses

1103 Oaklands Dr, Round Rock, TX 78681    512-3101271    512-2481221   

Mesa, AZ   

Plano, TX   

Sunnyvale, CA   

Dallas, TX   

Los Angeles, CA   

Torrance, CA   

Austin, TX   

Social networks

Stuart L Litwin

Linkedin

Work

Company: Litwin quality consulting Oct 2017 Position: Owner

Education

Degree: Bachelors, Bachelor of Science School / High School: Massachusetts Institute of Technology 2006 to 2006

Skills

Semiconductor Industry • Design of Experiments • Yield • Spc • Product Engineering • Process Integration • Semiconductors • Jmp • Flash Memory • Failure Analysis • Six Sigma • Fmea • Ic • Manufacturing • Characterization • Silicon • Semiconductor Process • Cmos • Asq • Metrology • Photolithography • Plasma Etch • Cvd • Device Characterization • Soc • Pecvd • Reliability • R&D • Analog • Mixed Signal • Statistical Process Control • Asq Certified 6 Sigma Black Belt • Thin Films • Pvd • Engineering Management • Cross Functional Team Leadership • Integrated Circuits • Iso/Ts16949 Trained Certified Auditor

Ranks

Certificate: Six Sigma Black Belt

Interests

Politics

Industries

Semiconductors
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Mentions for Stuart L Litwin

Stuart Litwin resumes & CV records

Resumes

Stuart Litwin Photo 12

Owner

Location:
1103 Oaklands Dr, Round Rock, TX 78681
Industry:
Semiconductors
Work:
Litwin Quality Consulting
Owner Sqa Services, Inc.
Associate Litwin Consulting
Sole Proprietor Towerjazz Feb 2016 - Apr 2016
Fab Quality Manager Maxim Integrated Sep 2013 - Jan 2016
Fab Quality Manager Spansion 1998 - Jul 2013
Senior Member of the Technical Staff Amd 1998 - 2005
Integration Engineer Spansion 1998 - 2000
Process Integration Engineer Cypress Semiconductor Corporation 1994 - 1997
Integration Engineer International Rectifier 1987 - 1994
Design Engineering Manager Freescale Semiconductor 1981 - 1987
Process and Device Engineer
Education:
Massachusetts Institute of Technology 2006 - 2006
Bachelors, Bachelor of Science Massachusetts Institute of Technology 1976 - 1981
Bachelors, Bachelor of Science, Chemical Engineering St. Mark's School of Texas
Skills:
Semiconductor Industry, Design of Experiments, Yield, Spc, Product Engineering, Process Integration, Semiconductors, Jmp, Flash Memory, Failure Analysis, Six Sigma, Fmea, Ic, Manufacturing, Characterization, Silicon, Semiconductor Process, Cmos, Asq, Metrology, Photolithography, Plasma Etch, Cvd, Device Characterization, Soc, Pecvd, Reliability, R&D, Analog, Mixed Signal, Statistical Process Control, Asq Certified 6 Sigma Black Belt, Thin Films, Pvd, Engineering Management, Cross Functional Team Leadership, Integrated Circuits, Iso/Ts16949 Trained Certified Auditor
Interests:
Politics
Certifications:
Six Sigma Black Belt
Iso/Ts 16949 Lead Auditor
American Society of Quality
Omnex Inc

Publications & IP owners

Us Patents

Floating Gate Process Methodology

US Patent:
7745236, Jun 29, 2010
Filed:
Dec 21, 2006
Appl. No.:
11/614767
Inventors:
Charles Ray Mathews - Austin TX, US
Alex Bierwag - Austin TX, US
Stuart Litwin - Round Rock TX, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/66
US Classification:
438 14, 438593, 257E29129
Abstract:
A method of deprocessing a semiconductor structure is provided. The method involves removing a silicide layer over a second poly layer, an interpoly dielectric layer, a first poly layer, an optionally an oxide layer on a substrate. The method may further involve at least one of removing a second poly layer, removing an interpoly dielectric layer, removing a first poly layer, removing an oxide layer, and removing an unimplanted portion of a substrate. The exposed layer/portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Copper Process Methodology

US Patent:
2008015, Jun 26, 2008
Filed:
Dec 21, 2006
Appl. No.:
11/614770
Inventors:
Charles Ray Mathews - Austin TX, US
Alex Bierwag - Austin TX, US
Stuart Litwin - Round Rock TX, US
Assignee:
SPANSION LLC - Sunnyvale CA
International Classification:
H01L 21/66
US Classification:
438 16, 257E2153
Abstract:
A method of deprocessing a semiconductor structure is provided. The method involves removing one or more interlevel dielectric layers and one or more metal components from a frontside of the semiconductor structure. By removing the interlevel dielectric layer and the metal component, the exposed portion of the semiconductor structure can be subjected to an inspection for defects and/or other characteristics by using an inspection tool. The inspection can aid in defect reduction strategies, among other things, when applied to new technology ramp, monitoring of baseline wafer starts, customer returns, etc.

Possible Relatives

David J Litwin  Daniel J Litwin  Dennis W Litwin  Diane Litwin  Dorothy J Litwin  Edward Litwin  Ethan E Litwin  Stuart B Johnson  Stuart B White  Stuart M Jones 

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