Sundar S Rajan, 5510834 E Ests Dr, Cupertino, CA 95014

7334074, Feb 19, 2008

Sep 8, 2006

11/518122

Sundar Rajan - Mountain View CA, US

Broadcom Corporation - Irvine CA

G06F 13/36

710315, 710306, 710310, 710311

A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

8379639, Feb 19, 2013

Jul 22, 2009

12/507169

Debojyoti Dutta - Santa Clara CA, US
Sumeet Singh - Mountain View CA, US
Pradeep Sudame - Fremont CA, US
Sundar Rajan - Palo Alto CA, US

Cisco Technology, Inc. - San Jose CA

H04L 12/28

370389, 370392, 726 22, 726 23

Apparatuses, methods, and other embodiments associated with packet identification are described. One example apparatus includes a packet selection logic to identify packets associated with a data stream. The example apparatus may also include a set of packet classification logics. A packet classification logic may generate a signal as a function of whether an attribute associated with the packet matches an attribute associated with packets generated by a tested application.

5923868, Jul 13, 1999

Oct 23, 1997

8/957003

Hagop A. Nazarian - San Jose CA
Stephen M. Douglass - Saratoga CA
W. Alfred Graf - Saratoga CA
S. Babar Raza - Sunnyvale CA
Sundar Rajan - Mountain View CA
Shiva Sorooshian Borzin - Fremont CA
Darren Newman - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

G06F 15173
G06F 1716

395500

Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w. sub. mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w. sub. mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

5689686, Nov 18, 1997

Mar 21, 1997

8/822769

Hagop A. Nazarian - San Jose CA
Stephen M. Douglass - Saratoga CA
W. Alfred Graf - Saratoga CA
S. Babar Raza - Sunnyvale CA
Sundar Rajan - Mountain View CA
Shiva Sorooshian Borzin - Fremont CA
Darren Neuman - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H04Q 304

395500

Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w. sub. mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w. sub. mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

5848066, Dec 8, 1998

Aug 30, 1996

8/705990

Hagop A. Nazarian - San Jose CA
Stephen M. Douglass - Saratoga CA
W. Alfred Graf - Saratoga CA
S. Babar Raza - Sunnyvale CA
Sundar Rajan - Mountain View CA
Shiva Sorooshian Borzin - Fremont CA
Darren Neuman - San Jose CA

Cypress Semiconductor Corp. - San Jose CA

H04Q 1104

370380

Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w. sub. mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w. sub. mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

5940596, Aug 17, 1999

Aug 4, 1997

8/905440

Sundar Rajan - Santa Clara CA
Kent Blair Dahlgren - San Jose CA

I-Cube, Inc. - Campbell CA

G06F 15163

39520072

A network switch forwards data packets between network stations connected to its input and output ports. Each data packet includes the network address of a destination station. The receiving input port consults an address translation system including a local address translation cache within each input port for caching recently used address-to-port translation information, a set of secondary address translation units each serving a separate cluster of input ports for caching a larger amount of recently used address translation information, and a main address translation unit storing address-to-port translation information for all network stations. An input port not having appropriate translation information in its local cache sends an address translation request to a secondary address translation unit. A secondary address translation unit not having appropriate address translation information to respond to the request, forwards the request to the main address translation unit. The main address translation unit returns the appropriate address translation information to the secondary address translation unit which caches that information and returns it to the requesting input port.

6243664, Jun 5, 2001

Oct 27, 1998

9/181084

Hagop A. Nazarian - San Jose CA
Stephen M. Douglass - Saratoga CA
W. Alfred Graf - Saratoga CA
S. Babar Raza - Sunnyvale CA
Sundar Rajan - Mountain View CA
Shiva Sorooshian Borzin - Fremont CA
Darren Neuman - San Jose CA

Cypress Semiconductor Corporation - San Jose CA

G06F 15173
G06F 1716

703 14

Methods for designing a programmable interconnect matrix having reduced connectivity to achieve maximum routability for the reduced connectivity. An array of multiplexors, each having a multiplexor width w. sub. mux that is less than number of input conductors for the programmable matrix, are coupled to the input conductors of the programmable interconnect matrix such that the number of input signals shared between any two multiplexors is less than the multiplexor width w. sub. mux and such that each input signal has approximately the same number of chances to route. To better ensure the successful routing of input signals by a programmable interconnect matrix designed according to the present methods, improved routing methods are also described. According to a first embodiment, routing is accomplished by swapping successfully routed input signals with a blocked input signal and determining whether the input signal that has been swapped out may be routed through available multiplexors. According to a second embodiment, a predictive swapping technique is used whereby successfully routed signals qualified to provide a blocked signal with a route are first checked to determine whether a successful routing will be provided before swapping in the blocked output signal.

2019032, Oct 24, 2019

Apr 20, 2018

15/958567

- Mountain View CA, US
Madhusudan Krishnan Iyengar - Foster City CA, US
Sundar Rajan - Mountain View CA, US
Jorge Padilla - Union City CA, US
Norman Paul Jouppi - Palo Alto CA, US

H05K 7/20

A data center cooling system includes a server rack sub-assembly that includes a motherboard mounted on a support member and a heat generating electronic devices mounted on the a motherboard; a cold plate positioned in thermal communication with at least a portion of the heat generating electronic devices, the cold plate configured to receive a flow of a cooling liquid circulated through a supply conduit fluidly coupled to a liquid inlet of the cold plate, through the cold plate, and through a return conduit fluidly coupled to a liquid outlet of the cold plate; and a modulating control valve attached to either of the motherboard or the support member and positioned in either of the supply conduit or the return conduit, the modulating control valve configured to adjust a rate of the flow of the cooling liquid based on an operating condition of at least one of the heat generating electronic devices.