Lam Sy Dong, 5534288 Pinnacles Dr, Union City, CA 94587

6725314, Apr 20, 2004

Mar 30, 2001

09/823540

Lam S. Dong - Union City CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1300

710305

A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.

6944738, Sep 13, 2005

Apr 16, 2002

10/123398

Lam S. Dong - Union City CA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F012/00

711167, 711105, 713322

A memory subsystem and a method for use in accessing a memory system are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a memory controller. The memory controller is capable of waiting to generate a memory clock signal for each of the SDRAM memory modules until a valid window for a control signal and an address signal; generating the memory clock signals during the valid window, and generating the control and address signals. The method comprises: waiting for a valid window for a control signal and an address signal; generating a memory clock during the valid window; and generating the control signal and the command signal a predetermined period of time after generating the memory clock signal.

2002016, Nov 7, 2002

May 1, 2001

09/846873

Lam Dong - Union City CA, US
Drew Doblar - San Jose CA, US

H05K007/00
H05K001/14

361/728000

A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.

2003009, May 15, 2003

Jun 14, 2002

10/171867

Drew Doblar - San Jose CA, US
Han Ko - Milpitas CA, US
Lam Dong - Union City CA, US
Clement Fang - Cupertino CA, US
David Jeffrey - Santa Cruz CA, US
Tayung Wong - Fremont CA, US
Jay Robinson - Sunnyvale CA, US
John Carrillo - San Jose CA, US
Nagaraj Mitty - San Jose CA, US
Nikhil Vaidya - San Francisco CA, US

H05K007/00
G06F012/00

361/728000, 711/167000

A memory module for expanding memory of a computer. The memory module comprises a printed circuit board including a connector edge having a plurality of contact pads configured to convey data signals, power and ground to and from said printed circuit board. The power and ground contact pads alternate along said connector edge with no more than four adjacent data signal contact pads without intervening power or ground contact pads. A plurality of memory devices mounted on the printed circuit board. A clock driver is coupled to each of the plurality of memory devices and is configured to receive a differential clock signal and to produce at least one single-ended clock signal for clocking the plurality of memory devices. The clock driver includes a phase-locked loop for phase-locking the at least one single-ended clock signal.