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Takeshi Watanabe, 4923 Pin Oak Ct, Westport, CT 06880

Takeshi Watanabe Phones & Addresses

23 Pin Oak Ct, Westport, CT 06880    203-2267957   

New York, NY   

Saddle River, NJ   

Education

School / High School: University of Chicago Law School

Ranks

Licence: New York - Currently registered Date: 1997

Mentions for Takeshi Watanabe

Career records & work history

Lawyers & Attorneys

Takeshi Watanabe Photo 1

Takeshi Watanabe - Lawyer

Address:
Anderson Mori & Tomotsune
368-881052x (Office)
Licenses:
New York - Currently registered 1997
Education:
University of Chicago Law School

Takeshi Watanabe resumes & CV records

Resumes

Takeshi Watanabe Photo 19

Assistant Professor

Location:
New York, NY
Industry:
Higher Education
Work:
Wesleyan University
Assistant Professor
Connecticut College Sep 2006 - Jun 2016
Visiting Assistant Professor
Wesleyan University 2012 - 2014
Visiting Assistant Professor
Education:
Yale University 1993 - 2005
Bachelors, Bachelor of Arts, Comparative Literature, Music
Yale University
Doctorates, Doctor of Philosophy, Japanese Literature, Japanese
Skills:
Research, Editing, Public Speaking, Academic Writing, Higher Education, Teaching, Tutoring, Grant Writing, Curriculum Design
Takeshi Watanabe Photo 20

Owner

Location:
New York, NY
Industry:
Program Development
Work:
Attob.com
Owner
Skills:
Seo, Sem, Website Development, Web Marketing, Php, Mysql, Jquery, Javascript, Html, Css
Takeshi Watanabe Photo 21

Takeshi Watanabe

Takeshi Watanabe Photo 22

Takeshi Watanabe

Publications & IP owners

Us Patents

Semiconductor Device And Manufacturing Method Thereof

US Patent:
7692303, Apr 6, 2010
Filed:
May 24, 2007
Appl. No.:
11/802613
Inventors:
Takeshi Watanabe - Somers NY, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
H01L 23/52
US Classification:
257754, 257204, 257206, 257377, 257755, 257769, 438587, 438630, 438655, 438664, 438682
Abstract:
A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

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