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Tarek M Taha1191 Red Ash Ct, Dayton, OH 45458

Tarek Taha Phones & Addresses

1191 Red Ash Ct, Dayton, OH 45458    937-8854186   

Washington Township, OH   

113 Nettles Rd, Clemson, SC 29631    864-6545044   

416 Rock Creek Rd, Clemson, SC 29631    864-6545044   

1191 Red Ash Ct, Dayton, OH 45458   

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Tarek M Taha

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Work

Company: Touch Feb 2014 Position: Trainee

Education

School / High School: Jadra campus 2010 Specialities: Bachelors in Computer and Communication engineer
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Career records & work history

Medicine Doctors

Tarek Taha

Specialties:
Orthopaedic Surgery
Work:
Saint Marys Of Michigan Orthopedic Associates
4701 Towne Ctr Rd STE 303, Saginaw, MI 48604
989-7906719 (phone) 989-7909464 (fax)
Education:
Medical School
Medical University of South Carolina College of Medicine
Graduated: 2007
Procedures:
Shoulder Arthroscopy, Arthrocentesis, Carpal Tunnel Decompression, Hip Replacement, Hip/Femur Fractures and Dislocations, Joint Arthroscopy, Knee Replacement, Lower Arm/Elbow/Wrist Fractures and Dislocations, Occupational Therapy Evaluation, Shoulder Surgery
Languages:
English
Description:
Dr. Taha graduated from the Medical University of South Carolina College of Medicine in 2007. He works in Saginaw, MI and specializes in Orthopaedic Surgery. Dr. Taha is affiliated with Covenant Healthcare and St Marys Of Michigan Medical Center.
Tarek Taha Photo 1

Tarek Assaad Taha

Specialties:
Orthopaedic Surgery

Tarek Taha resumes & CV records

Resumes

Tarek Taha Photo 33

Tarek Taha

Tarek Taha Photo 34

Tarek Taha

Work:
Touch Feb 2014 to Mar 2014
trainee Glassline Industries Jul 2013 to Dec 2013
site engineer in Aluminum fabrication Glassline Industries Jan 2011 to Jun 2012 Wardeh Company Nov 2010 to Apr 2011
sales in different
Education:
Jadra campus 2010 to 2014
Bachelors in Computer and Communication engineer

Publications & IP owners

Us Patents

Analog Neuromoprhic Circuit With Stacks Of Resistive Memory Crossbar Configurations

US Patent:
2023002, Jan 26, 2023
Filed:
Jul 25, 2022
Appl. No.:
17/872626
Inventors:
- Dayton OH, US
Tarek M. Taha - Centerville OH, US
Chris Yakopcic - Dayton OH, US
International Classification:
G06N 3/063
G11C 11/54
G11C 13/00
Abstract:
An analog neuromorphic circuit is disclosed having a resistive memory crossbar configurations positioned in the analog neuromorphic circuit forming a 3D stack. Input voltages are applied to an input selector unit that selects a first selected resistive memory crossbar configuration that the input voltages are applied. Output voltages are generated by the first selected resistive memory crossbar configuration from a propagation of the input voltages through resistive memories positioned on the first selected resistive memory crossbar configuration. An output selector unit selects the first selected resistive memory crossbar configuration that generates the output voltages. Each output voltage corresponds to an output of the first selected resistive memory crossbar configuration as selected by the output selector. An activation function unit receives the output voltages generated from the first selected memory crossbar configuration and executes a function based on the output voltages received from the first selected resistive memory crossbar configuration.

Analog Neuromorphic Circuit Implemented Using Resistive Memories

US Patent:
2021032, Oct 21, 2021
Filed:
Jun 29, 2021
Appl. No.:
17/362272
Inventors:
- Dayton OH, US
Md Raqibul Hasan - Baltimore MD, US
Tarek M. Taha - Centerville OH, US
International Classification:
G06N 3/063
G11C 11/54
G11C 13/00
Abstract:
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Analog Neuromorphic Circuits For Dot-Product Operation Implementing Resistive Memories

US Patent:
2021032, Oct 21, 2021
Filed:
Jun 30, 2021
Appl. No.:
17/364019
Inventors:
- Dayton OH, US
Tarek M. Taha - Centerville OH, US
Md Raqibul Hasan - Baltimore MD, US
International Classification:
G06N 3/063
G11C 11/54
G11C 13/00
G06F 17/10
G06N 3/08
G06N 3/04
Abstract:
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Satisfiability Problem Solver Implemented On Spiking Neural Network Embedded Systems

US Patent:
2021001, Jan 21, 2021
Filed:
Jul 20, 2020
Appl. No.:
16/933994
Inventors:
- Dayton OH, US
Tarek M. Taha - Centerville OH, US
International Classification:
G06N 3/04
Abstract:
A spiking neural network (SNN) system is disclosed having spiking neurons associated with clause values associated with a satisfiability (SAT) problem. Each spiking neuron generates a voltage spike when on input voltage applied to each spiking neuron is increased above a spiking voltage threshold. The input voltage that is increased above the spiking voltage threshold is indicative that the corresponding clause value is satisfied. A controller applies the clause grid that includes clause values to a literal grid that includes literal values. The controller generates the input voltage that is applied to each spiking neuron based on each corresponding clause value associated with each spiking neuron that is applied to the literal values. The controller determines that each clause value is satisfied when the corresponding spiking neuron generates the voltage spike and that each clause value is unsatisfied when the corresponding spiking neuron fails to generate the voltage spike.

Analog Neuromorphic Circuits For Dot-Product Operation Implementing Resistive Memories

US Patent:
2021001, Jan 21, 2021
Filed:
Sep 29, 2020
Appl. No.:
17/036533
Inventors:
- Dayton OH, US
Tarek M. Taha - Centerville OH, US
Md Raqibul Hasan - Baltimore MD, US
International Classification:
G06N 3/063
G11C 11/54
G11C 13/00
G06F 17/10
G06N 3/08
G06N 3/04
Abstract:
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrixvalues included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in theweighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Analog Neuromorphic Circuit Implemented Using Resistive Memories

US Patent:
2020036, Nov 19, 2020
Filed:
Jun 1, 2020
Appl. No.:
16/889177
Inventors:
- Dayton OH, US
Md Raqibul Hasan - Baltimore MD, US
Tarek M. Taha - Centerville OH, US
International Classification:
G06N 3/063
G11C 11/54
G11C 13/00
Abstract:
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Analog Neuromorphic Circuit Implemented Using Resistive Memories

US Patent:
2020007, Mar 5, 2020
Filed:
Nov 11, 2019
Appl. No.:
16/679800
Inventors:
- Dayton OH, US
Md Raqibul Hasan - Baltimore MD, US
Tarek M. Taha - Centerville OH, US
International Classification:
G06N 3/063
G11C 13/00
G11C 11/54
Abstract:
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Analog Neuromorphic Circuits For Dot-Product Operation Implementing Resistive Memories

US Patent:
2019033, Oct 31, 2019
Filed:
Jul 9, 2019
Appl. No.:
16/506145
Inventors:
- Dayton OH, US
Tarek M. Taha - Centerville OH, US
Md Raqibul Hasan - Baltimore MD, US
International Classification:
G06N 3/063
G11C 11/54
G06F 17/10
G11C 13/00
G06N 3/08
G06N 3/04
Abstract:
An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Possible Relatives

Danny S Taha  Abdallah R Taha  Abe Taha  Hanni A Taha  Hassan Taha  Issam A Taha  Jamal K Taha  Tarek Moussa  Tarek S Salama  Tarek S Salem 

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