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Tarmo Juri Tammaru, 47476 Adirondack Ave, Spotswood, NJ 08884

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476 Adirondack Ave, Spotswood, NJ 08884    732-2514493   

Highland Park, NJ   

Work

Position: Precision Production Occupations

Education

Degree: Associate degree or higher

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Publications & IP owners

Us Patents

Data Scrambler

US Patent:
4304962, Dec 8, 1981
Filed:
Aug 25, 1965
Appl. No.:
4/482498
Inventors:
Renato D. Fracassi - Middletown NJ
Tarmo Tammaru - Red Bank NJ
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
H04L 900
US Classification:
178 2212
Abstract:
Binary digital data signal patterns containing either no transitions, periodically recurring transitions or both are randomized by constructing a key signal from a summation of selected stored digits of the data pattern and combining such key signal with the data signal to form a scrambled line signal for transmission. The line signal so constructed is free of signal energy concentrated at particular frequencies and provides signal transitions adequate in number to assure reliable recovery of synchronization information. Descrambling of the received line signal is accomplished by precisely the inverse of the scrambling operation. The system is self-synchronizing because the key signals constructed by each of the scrambler and descrambler are derived from the same line signal.

One-Bit-Out-Of-N-Bit Checking Circuit

US Patent:
4087786, May 2, 1978
Filed:
Dec 8, 1976
Appl. No.:
5/748654
Inventors:
Frank William Lescinsky - Middletown NJ
Tarmo Tammaru - Middletown NJ
Assignee:
Bell Telephone Laboratories, Incorporated - Murray Hill NJ
International Classification:
G06F 1108
US Classification:
3401461AB
Abstract:
A one-bit-out-of-n bit checking circuit is comprised of k serially connected detector levels. A first one of the detector levels accommodates n input signal lines and successively higher ones of the detector levels have one half the number of input signal lines as does the next lower detector level. Each detector level is comprised of a plurality of logic blocks with each logic block being connected to a separate pair of input signal lines. Each logic block in each level detects the presence of excitation signals on both input signal lines of the pair of input signal lines and generates an error signal in response thereto. Each logic block also detects the presence of an excitation signal on one input signal line of the pair of input signal lines and in response thereto propagates the excitation signal through successively higher detector levels to the k. sup. th detector level. The k. sup. th detector level generates an excitation signal output in response to the presence of an excitation signal on one and only one of the input signal lines applied to the k. sup. th level.

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